Semiconductor Debug Selector Switching for Minimal Overhead Access
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Solution Overview
Problem
Existing debug systems for semiconductor apparatuses require complex configurations and incur significant overhead, including CPU suspension, due to the need for DMA controllers and bus arbitration circuits, which enlarges the circuit scale and increases clock overhead, making them unsuitable for applications where minimal disruption is essential.
Innovation Solution
A semiconductor apparatus with a selector and debug control portion that allows external access to internal resources without CPU suspension by temporarily switching between select states, enabling read and write operations with minimal overhead, using a selector to manage access between the CPU and debug control portions, and a state machine to control program execution states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a DMA controller and bus arbitration circuit are added to enable external access to internal resources, then the debug functionality is improved, but the circuit scale is enlarged
Solution Approach 1:
The patent extracts the essential debug functionality from complex DMA controllers and bus arbitration circuits, implementing only the minimal necessary components: a selector that can switch between CPU access and debug access, and a debug control portion. This extraction eliminates unnecessary complexity while preserving the core capability of external access to internal resources.
Solution Approach 2:
The selector is designed to serve multiple functions: it acts as a CPU access gate during normal operation and as a debug access gate when switched to the other state. This multi-functionality eliminates the need for separate dedicated circuits for CPU and debug access, reducing overall circuit scale while maintaining both functionalities.
2Ease of operation
If a bus arbitration circuit is provided to manage CPU and debugger memory access, then access control is improved, but the circuit scale is enlarged
Solution Approach 1:
The patent extracts only the essential access control functionality needed for debugging, implementing a simple selector with two states instead of a full bus arbitration circuit. The selector directly switches between CPU access and debug access without the overhead of complex arbitration logic, achieving access control with minimal circuitry.
3Measurement precision
If the CPU is suspended to access internal resources from outside, then access accuracy is improved, but program execution is disrupted
Solution Approach 1:
The patent implements a dynamic switching mechanism where the selector can be temporarily switched to allow debug access and then restored to its original state. This dynamic approach enables accurate access to internal resources while minimizing disruption to program execution, as the CPU can resume immediately after the temporary switch.
Solution Approach 2:
The patent uses a state machine to preliminarily control the switching sequence, ensuring that the selector is switched only when appropriate and restored immediately after access. This preliminary control prevents unnecessary CPU suspension and maintains program execution flow while enabling accurate debug access when needed.
4Adaptability or versatility
If interrupt process is entered to perform debug operation, then debug capability is improved, but clock overhead is increased
Solution Approach 1:
The patent extracts the essential debug capability from complex interrupt-driven debug systems, implementing a direct selector-switching mechanism. This eliminates the need for interrupt processes and associated clock overhead, providing debug capability through simple state transitions that minimize time loss.
Solution Approach 2:
The patent skips the intermediate step of entering an interrupt process by directly switching the selector state for debug access. This rushing through the access process eliminates the clock overhead associated with interrupt entry and exit, enabling fast debug operations with minimal impact on program execution timing.
Data Source
AI summary
It is an object of the present invention to provide a debug system that accesses a semiconductor apparatus from the outside by a simple configuration at less overhead.The present invention relates to a semiconductor apparatus and a debug system. A large scale integration (LSI 11) includes a central processing unit (CPU 20), a debug control portion (21), an internal bus (22), a storage portion (23, 24, 26) connected to the internal bus, and a selector (27). According to a select control signal (CNT) from the CPU, the selector selects either a CPU select state of transmitting a signal from the CPU to the internal bus, or a debugger select state of transmitting a signal from the debug control portion to the internal bus. In principle, the selector is set to the CPU select state. Upon receiving a predetermined command from an external device (12, 13) by the debug control portion, a signal corresponding to the predetermined command is sent from the debug control portion to the CPU, and the selector is temporarily set to the debugger select state, thereby accessing the internal bus through the debug control portion.