Semiconductor Device Deep Short Slit Etching
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Solution Overview
Problem
As semiconductor devices downscale, the pinch-off of conductive layers during filling and formation leads to increased resistance values and voids in conductive layers, posing challenges in maintaining low resistance and high patterning precision in three-dimensional stacked memory structures.
Innovation Solution
The introduction of deep and short slits within the stacked body, in addition to traditional deep slits, allows for more efficient removal of sacrificial films and improved diffusion of metal precursors, reducing the resistance value of conductive layers and enhancing patterning precision by altering the etching path and metal deposition processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional filling and formation processes are used for conductive layers in downscaled memory cells, then manufacturing simplicity is maintained, but resistance value increases and voids occur in conductive layers
Solution Approach 1:
The patent divides the single deep slit into multiple deep slits and introduces additional short slits, segmenting the etching path into multiple sections. This segmentation allows metal precursors to diffuse from multiple entry points, ensuring complete filling of conductive layers without voids and maintaining low resistance values in downscaled structures
Solution Approach 2:
The patent transitions from a single-dimensional deep slit structure to a multi-dimensional network of deep slits and short slits. The short slits extend in the depth direction from the upper surface, creating additional diffusion pathways that intersect with the deep slits, enabling comprehensive metal precursor distribution throughout the conductive layer formation region
2Productivity
If deep slits are used for sacrificial film removal, then etching efficiency is improved, but metal precursor diffusion is insufficient leading to voids in conductive layers
Solution Approach 1:
The patent segments the single deep slit into multiple deep slits and complements them with short slits, creating a distributed network of etching and diffusion pathways. This segmentation ensures that metal precursors can reach all regions of the conductive layer formation area through multiple routes, eliminating voids while maintaining efficient sacrificial film removal
Solution Approach 2:
The short slits act as intermediary structures that connect the upper surface to the deep slit regions. They provide intermediate diffusion pathways that facilitate metal precursor transport into the deep regions where conductive layers form, ensuring complete filling without compromising the efficiency of sacrificial film removal through the deep slits
3Quantity of substance
If conductive layers are formed in downscaled memory cells, then memory cell density is increased, but pinch-off occurs during filling leading to increased resistance
Solution Approach 1:
The patent introduces short slits that extend in the depth direction from the upper surface, creating a multi-dimensional diffusion network. This additional dimensionality ensures that metal precursors can reach deeply into the downscaled conductive layer formation regions, preventing pinch-off and maintaining low resistance values even as memory cell density increases
Solution Approach 2:
The patent replaces the conventional single-path mechanical filling approach with a multi-path diffusion-based approach. By introducing multiple deep slits and short slits, the system uses diffusive transport from multiple entry points to ensure complete and uniform filling of conductive layers in downscaled structures, avoiding pinch-off phenomena
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively suppresses the increase in resistance value of conductive layers and improves the precision of the stacked body formation, enabling the creation of low-resistance conductive layers and maintaining designed dimensions, thereby enhancing the performance and reliability of semiconductor devices.
Implementation Method 1
altering the etching path and metal deposition processes
Implementation Method 2
improved diffusion of metal precursors
Data Source
AI summary
According to one embodiment, a semiconductor device includes a stacked body, first, second, third, and fourth insulating bodies, first and second columnar portions. The stacked body includes a conductive layer and an insulating layer stacked alternately. The first, second, third and fourth insulating bodies, the first and second columnar portions are provided inside the stacked body. The second insulating body is at a position different from the first insulating body. The third insulating body is between the first and second insulating bodies. The fourth insulating body is between the first and second insulating bodies, and includes portions contacting the third insulating body and being separated from each other with the third insulating body interposed. The first columnar portion is between the first and fourth insulating bodies. The second columnar portion is between the second and fourth insulating bodies. The first and second columnar portions include a semiconductor layer.