Semiconductor Device Deep Trench Isolation for CD Uniformity
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Solution Overview
Problem
The semiconductor industry faces challenges in achieving high critical dimension (CD) uniformity in densely packed active regions, which is crucial for advanced device integration and performance.
Innovation Solution
The approach involves forming a semiconductor device with a substrate that includes a cell array region and a peripheral circuit region, utilizing trench isolation regions with recessed deep trenches in the peripheral circuit region to create high CD uniformity, and employing specific masking and etching processes to define active regions with precise dimensions and spacing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If device isolation regions are reduced in size to increase integration density, then integration density improves, but critical dimension uniformity deteriorates
Solution Approach 1:
The patent applies local quality by creating deep trench isolation regions at specific locations between active regions where CD uniformity needs improvement. These deep trenches are not uniformly distributed but strategically placed in areas where spacing variations occur, providing enhanced isolation and consistent CD control locally without increasing overall device size, thus resolving the contradiction between integration density and manufacturing precision.
2Productivity
If active regions are densely packed to improve integration, then integration density improves, but spacing uniformity deteriorates
Solution Approach 1:
The patent employs preliminary action by forming deep trench isolation regions before final active region patterning. This preliminary isolation structure pre-establishes uniform spacing references that guide subsequent fabrication steps, ensuring that even as active regions are densely packed, their spacing remains uniform. The deep trenches act as pre-formed spacers that maintain consistent dimensions throughout the manufacturing process.
Data Source
AI summary
According to an example embodiment, a semiconductor device includes a substrate having a cell array region and a peripheral circuit region. The substrate includes first active regions defined by a first trench isolation region in the cell array region, a second active region defined by a second trench isolation region in the peripheral circuit region, and at least one deep trench isolation region. The first active regions may be aligned to extend longitudinally in a first direction in the cell array region. The at least one deep trench isolation region is recessed in the substrate to a level lower than those of other points of a bottom surface of the second trench isolation region in the peripheral circuit region. The at least one deep trench isolation region includes at least one point that is spaced apart in the first direction from a corresponding one of the first active regions.