Semiconductor Device Deep Well Region High Voltage Blocking
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing high-switching power devices struggle to effectively withstand high voltages, such as several hundred volts, while maintaining efficient operation and simple fabrication processes.
Innovation Solution
A semiconductor device is fabricated with a specific structure including a semiconductor substrate, well regions, doping regions, and isolation elements, where thermal annealing forms a deep well region to enhance blocking voltage and reduce pinch-off voltage, and the device can be configured as either a lateral JFET or Schottky diode for high-voltage applications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing high-switching power devices are used, then switching efficiency is maintained, but blocking voltage capability is insufficient
Solution Approach 1:
The device structure is segmented into multiple well regions (first well region with second conductive type, second well region with second conductive type, and pair of third well regions with first conductive type) separated by isolation elements. This segmentation allows each region to perform specific functions for voltage blocking while maintaining a systematic fabrication approach that doesn't significantly increase process complexity
Solution Approach 2:
Different conductive types are localized in different regions: the first conductive type in the semiconductor layer and third well regions, and the second conductive type in the first well region, second well region, and deep well region. This local quality differentiation enables precise control of electric field distribution to achieve high blocking voltage capability
2Reliability
If high voltage withstanding capability is improved, then power handling increases, but device structure becomes more complex
Solution Approach 1:
The device employs a nested well structure where the deep well region (second conductive type) is formed in the semiconductor substrate, and above it are the first well region and second well region (both second conductive type) in the semiconductor layer, with third well regions (first conductive type) positioned between them. This nesting achieves high voltage blocking through multiple concatenated junctions without requiring entirely separate device structures
Solution Approach 2:
The patent transitions from planar device structures to vertical dimensionality by forming deep well regions in the substrate and multiple well regions in the epitaxial layer at different depths and horizontal positions. This vertical stacking creates multiple blocking junctions in series, significantly enhancing voltage withstanding capability while maintaining a compact footprint
3Productivity
If pinch-off voltage is reduced, then switching efficiency improves, but voltage control precision decreases
Solution Approach 1:
The patent optimizes doping concentrations in different regions to achieve the desired voltage characteristics. The third well regions (first conductive type) are doped at concentrations that create appropriate depletion regions for low pinch-off voltage, while the deep well region and first/second well regions (second conductive type) are doped to maintain precise voltage control. This parameter optimization enables both high switching efficiency and precise voltage control
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The semiconductor device achieves high blocking voltage and low pinch-off voltage, enabling it to handle high voltages while simplifying the fabrication process and eliminating the need for additional processes, making it suitable for high-switching power applications.
Implementation Method 1
performing a thermal annealing process to diffuse and connect the plurality of doping regions to form a deep well region
Data Source
AI summary
A semiconductor device includes a semiconductor substrate and a semiconductor layer formed thereon; a first well region disposed in a portion of the semiconductor layer; a second well region disposed in another portion of the semiconductor layer; a pair of third well regions disposed in a portion of the semiconductor layer at opposite sides of the second well region; a plurality of isolation elements disposed over the semiconductor layer, respectively between the third well regions and the first and second well region; a deep well region disposed in a portion of the semiconductor substrate adjacent to the semiconductor layer between the first and second well region; a first doping region disposed in the first well region; and second doping regions disposed in the third well regions.