Semiconductor Defect Classification via Layout Overlap Analysis
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Solution Overview
Problem
Conventional semiconductor defect classification methods fail to accurately identify the cause of layout-induced systematic defects due to errors in defect coordinates and the two-dimensional nature of defects, which complicates determining the state of overlap with design layout patterns.
Innovation Solution
A defect classifying apparatus that generates a defect shape image by comparing a defective image with a reference image, superimposes this image on design layout patterns for multiple layers, and determines the state of overlap to classify defects as within, over, or outside the pattern, using techniques such as area and outline ratio analysis.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If defect coordinates from inspection apparatus are used for classification, then classification process is simplified, but determination accuracy of defect-state-of-overlap deteriorates due to coordinate errors of several to over ten micrometers
Solution Approach 1:
The patent creates a copied representation of the defect by generating a defect shape image that captures the two-dimensional extent and morphology of the defect. This copied visual representation is then superimposed on the design layout pattern, allowing accurate determination of the defect-state-of-overlap without relying on precise point coordinates. The copying approach transforms the problem from coordinate-based classification to image-based classification, resolving the contradiction between operational simplicity and measurement precision.
2Productivity
If point-based defect coordinates are used, then processing is easier, but accurate determination of defect-state-of-overlap becomes difficult due to the two-dimensional nature of defects
Solution Approach 1:
The patent transitions from one-dimensional point coordinates to two-dimensional defect shape images by incorporating the spatial extent and morphology of defects. This dimensional expansion allows accurate determination of whether a defect is within, over, or outside a pattern by visually comparing the defect shape image with the design layout pattern. The dimensionality change resolves the contradiction by providing sufficient information for precise classification while maintaining automated processing efficiency.
3Ease of operation
If conventional ADC classification based on shape and brightness is used, then classification is straightforward, but identification of layout-induced systematic defect causes becomes impossible
Solution Approach 1:
The patent merges conventional ADC classification (based on shape and brightness) with layout pattern information by superimposing the defect shape image on the design layout pattern. This combination allows the system to maintain the simplicity of conventional classification while simultaneously determining the defect-state-of-overlap with the pattern. The merged approach enables identification of layout-induced systematic defect causes by revealing the spatial relationship between defects and design patterns, resolving the contradiction between classification straightforwardness and cause identification capability.
Data Source
AI summary
A defect is efficiently and effectively classified by accurately determining the state of overlap between a design layout pattern and the defect. This leads to simple identification of a systematic defect. A defective image obtained through defect inspection or review of a semiconductor device is automatically pattern-matched with design layout data. A defect is superimposed on a design layout pattern for at least one layer of a target layer, a layer immediately above the target layer, and a layer immediately below the target layer. The state of overlap of the defect is determined as within the pattern, over the pattern, or outside the pattern, and the defect is automatically classified.