Semiconductor Defect Correlation via Physical Map
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Solution Overview
Problem
Conventional methods for identifying physical defects in semiconductor devices during the manufacturing process are time-consuming and inefficient, often requiring access to electronic design software and personnel, which can delay production and increase costs due to the need for destructive testing and the involvement of device architects.
Innovation Solution
A suite of testing methods and feedback mechanisms that provide high granularity location information about potential physical defects, allowing for specific fault identification and localization within the silicon implementation without requiring full design information, using test circuits and logical simulation to refine candidate defect regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional methods are used to identify physical defects, then defect detection is possible, but the process is time-consuming and requires access to electronic design software and personnel
Solution Approach 1:
The patent creates a physical map that copies the essential spatial relationships of the semiconductor device structure without requiring access to the original electronic design software. This physical map serves as a standalone representation that enables defect location analysis independently, resolving the contradiction by providing accurate defect detection capability while eliminating the time loss associated with requiring design personnel and software access
Solution Approach 2:
The patent segments the failure analysis process into two independent components: (1) creation of a physical map from manufacturing data, and (2) correlation of test failures with the physical map. This segmentation allows the analysis to proceed without requiring access to electronic design software, thereby reducing turnaround time while maintaining defect detection accuracy
2Measurement precision
If conventional methods are used to identify physical defects, then defect location can be determined, but destructive testing is required which delays production
Solution Approach 1:
The physical map serves as a non-destructive copy of the device structure that enables precise defect location identification. By correlating test failure data with features on the physical map, the system can pinpoint defect locations without requiring destructive physical analysis, thereby maintaining high measurement precision while preserving production productivity
Solution Approach 2:
The patent implements a feedback mechanism where test failure results are correlated with the physical map to identify suspect regions. This feedback loop enables iterative refinement of defect location identification without destructive testing, allowing precise defect localization that maintains both measurement precision and production throughput
3Measurement precision
If full design information is used for defect analysis, then comprehensive defect identification is possible, but it requires involvement of device architects and increases costs
Solution Approach 1:
The patent extracts only the essential spatial and structural information needed for defect analysis from the complete design data, creating a simplified physical map. This extracted representation maintains sufficient detail for comprehensive defect identification while eliminating the complexity of requiring full design information and device architect involvement, thereby reducing system complexity without sacrificing defect identification completeness
Solution Approach 2:
The physical map acts as an intermediary between manufacturing data and defect analysis. It translates complex manufacturing process data into a simplified representation that can be directly correlated with test failures, serving as a mediator that enables comprehensive defect identification without requiring access to complex electronic design software or expert personnel
Data Source
AI summary
Various embodiments related to correlating a location of a defect on a substrate for a semiconductor device to an electrical significance of a device structure at that location are disclosed. For example, one embodiment includes receiving a defect location for the location on the substrate where the defect was detected; receiving a physical representation of the semiconductor device for the defect location; generating a significance determination indicating whether the defect is located in an electrically significant region by correlating the defect location to logical and physical layout information included in the physical representation; and displaying the significance determination.