Semiconductor Memory Defect Counting With Reduced-Width Output
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Solution Overview
Problem
Existing semiconductor storage devices face challenges in efficiently testing memory cell groups due to increased test time when all bits are assumed to pass, as current methods cannot count defects accurately without assuming all bits pass, making them unsuitable for memories where this assumption is not valid.
Innovation Solution
A semiconductor storage device with a memory cell array and a defect information obtaining unit that outputs defect information indicating the number of defects as 0 to n bits, using a defect number counter to provide different values for each number of defects, allowing for accurate defect counting without assuming all bits pass.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If test data is output without change via data output terminal, then all defect information is preserved, but test time increases due to outputting data by the number of memory cell groups
Solution Approach 1:
The patent extracts only the essential defect information (defect occurrence and defect number) from the complete test data, outputting this condensed information through a dedicated defect information output terminal rather than outputting all raw test data. This extraction principle reduces the data volume significantly while preserving the critical defect detection capabilities.
Solution Approach 2:
The patent introduces a defect information generation circuit as an intermediary component that processes the test data read from memory cell groups. This circuit generates condensed defect information (whether defect occurred and how many defects) which is then output separately from the original test data, acting as a mediator between the memory array and the external testing system.
2Ease of operation
If 0/1 determination is performed on all bits, then pass/fail determination is simple, but defect counting capability is lost and cannot apply to memories where not all bits must pass
Solution Approach 1:
The patent segments the defect information into two distinct pieces: (1) defect occurrence information indicating whether a defect exists, and (2) defect number information indicating how many defects are present. This segmentation allows the system to maintain simple pass/fail determination while simultaneously providing defect counting capability, making it adaptable to different memory testing requirements.
Solution Approach 2:
The patent changes the parameters of the output information from simple pass/fail binary determination to include additional parameters: defect occurrence (yes/no) and defect number (count). This parameter expansion enables the same circuit to support both simple pass/fail testing and detailed defect analysis, increasing versatility across different memory types and testing scenarios.
3Loss of time
If test data is compressed for each memory cell group, then output test data is reduced, but defect counting information is lost
Solution Approach 1:
The patent introduces a defect information generation circuit as an intermediary that processes compressed test data from memory cell groups and extracts meaningful defect information. This intermediary preserves defect counting capability by specifically analyzing the compressed data to determine defect occurrence and defect numbers, then outputting this preserved information separately.
Solution Approach 2:
The patent extracts defect-specific information (defect occurrence and defect number) from the compressed test data through the defect information generation circuit. This extraction process retrieves the essential defect counting information that would otherwise be lost in compression, maintaining this critical data in a condensed format suitable for efficient output.
Data Source
AI summary
There is provided a semiconductor storage device according to an embodiment includes a memory cell array including a plurality of memory cells; a read data output unit that outputs data read from the memory cell array to the outside with a bit width of m bits without changing the data; and a defect information obtaining unit that obtains defect information indicating a defect when the defect is detected in the data read from the memory cell array. The defect information obtaining unit outputs defect information, in which the number of defects in the data read from the memory cell array is 0 to n bits (n<m) bits, for outputting different values to the outside for each number of defects, with 2 to n bit values indicating 1-bit information, respectively.