Semiconductor Defect Detection Using Virtual Layout Images
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Solution Overview
Problem
As semiconductor integrated circuits become more integrated and line widths decrease, defect detection in these circuits becomes increasingly costly and time-consuming using traditional scanning electron microscope (SEM) imaging methods.
Innovation Solution
Implementing a processor-executed defect detection module that generates layout images from capture images using machine learning, aligns these images to detect defects, and analyzes process variations to improve detection accuracy and speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional SEM imaging methods are used to detect defects, then measurement precision is maintained, but productivity decreases and loss of time increases
Solution Approach 1:
The patent creates a virtual layout image that replicates the expected semiconductor circuit pattern from design data, then compares this copy with the actual SEM capture image to detect defects. This copying approach enables rapid comparison without requiring additional physical imaging, thus improving productivity while maintaining measurement precision through accurate defect detection via image differencing
Solution Approach 2:
The system performs preliminary generation of the virtual layout image from design data before the actual defect detection process. By preparing the reference layout image in advance, the system eliminates the need for time-consuming image processing during detection, thereby improving productivity while ensuring measurement precision through consistent reference comparison
2Measurement precision
If traditional SEM imaging methods are used to detect defects, then measurement precision is maintained, but loss of time increases
Solution Approach 1:
The patent creates a virtual layout image that replicates the expected semiconductor circuit pattern from design data, then compares this copy with the actual SEM capture image to detect defects. This copying approach enables rapid comparison without requiring additional physical imaging, thus improving productivity while maintaining measurement precision through accurate defect detection via image differencing
Solution Approach 2:
The system performs preliminary generation of the virtual layout image from design data before the actual defect detection process. By preparing the reference layout image in advance, the system eliminates the need for time-consuming image processing during detection, thereby improving productivity while ensuring measurement precision through consistent reference comparison
Data Source
AI summary
Disclosed is a semiconductor integrated circuit fabricating method of a semiconductor fabricating device which includes a processor executing a defect detection module includes receiving, at the defect detection module, a first capture image of the semiconductor integrated circuit and a first layout image, generating, at the defect detection module, a second layout image from the first capture image, generating, at the defect detection module, a contour image from the first capture image and the second layout image, detecting, at the defect detection module, a defect of the semiconductor integrated circuit based on the first layout image and the contour image, analyzing, at the semiconductor fabricating device, a correlation between a kind of the defect and process variations of the semiconductor integrated circuit, and changing, at the semiconductor fabricating device, at least one process variation having a correlation with the defect from among the process variations.