Semiconductor Defect Detection via Virtual Micro Area Segmentation
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Solution Overview
Problem
Current methods for detecting defective layers in semiconductor devices are time-consuming and lack accuracy, particularly in identifying specific defective layers amidst multiple layers in a semiconductor device.
Innovation Solution
A method involving a computing system that obtains candidate defective layer information and physical structure information, divides wires into virtual micro areas, and identifies defective layers based on the number of micro areas, utilizing failure diagnosis results, layer characteristics, and defect analysis information.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If physical defect analysis (PFA) is performed for defect analysis, then defect detection capability is improved, but turn-around time increases significantly
Solution Approach 1:
The patent segments the defect analysis process into two distinct phases: (1) a fast computational phase using layout-aware analysis to identify candidate defective layers and nets, and (2) a targeted physical analysis phase that focuses only on the identified candidates. This segmentation allows the majority of the analysis to be performed computationally without time-consuming physical intervention, while still maintaining high detection accuracy for the critical cases.
Solution Approach 2:
The patent performs preliminary computational analysis using layout-aware tools to identify candidate defective layers and nets before conducting physical defect analysis. This preliminary action filters down the scope of physical analysis to only those areas most likely to contain defects, significantly reducing the turn-around time while maintaining detection effectiveness.
2Productivity
If layout aware analysis is used to identify defective nets, then analysis speed is improved, but accuracy in identifying specific defective layers deteriorates
Solution Approach 1:
The patent segments the identification process into two stages: first using layout-aware analysis to identify candidate nets and layers quickly, then applying additional computational algorithms to these candidates to determine the specific defective layer. This two-stage segmentation maintains the speed advantage of layout-aware analysis while improving layer identification accuracy through focused computational analysis of the candidate set.
Solution Approach 2:
The patent introduces an intermediary computational analysis step that acts as a bridge between the fast but less precise layout-aware analysis and the accurate but slow physical defect analysis. This intermediary computational phase processes the candidate nets and layers identified by layout-aware tools, using additional algorithms and criteria to pinpoint the specific defective layer, thereby improving overall accuracy without sacrificing the initial speed advantage.
3Reliability
If multiple candidate defective layers are considered, then detection comprehensiveness is improved, but identification accuracy deteriorates due to difficulty in pinpointing the specific defective layer
Solution Approach 1:
The patent implements a feedback mechanism where the results from layout-aware analysis of multiple candidate layers are fed back into the computational analysis system. The system evaluates each candidate layer using multiple criteria and algorithms, and the feedback loop refines the identification process to progressively narrow down to the most likely defective layer, thereby maintaining comprehensiveness while improving identification accuracy.
Solution Approach 2:
The patent changes the parameters used for evaluating candidate defective layers by considering multiple factors including net complexity, layer characteristics, defect patterns, and computational metrics. By dynamically adjusting and weighing these parameters in the computational analysis, the system can differentiate between multiple candidates and identify the specific defective layer with higher accuracy, even when multiple layers are initially identified as candidates.
Data Source
AI summary
Provided is a method of detecting a defective layer. A method, performed by a computing system, of detecting a defective layer of a semiconductor device including a plurality of layers includes obtaining candidate defective layer information regarding a plurality of candidate defective layers and obtaining physical structure information regarding the candidate defective layers, dividing each of wires in the candidate defective layers into virtual micro areas based on the candidate defective layer information and based on the physical structure information, and identifying a defective layer from among the candidate defective layers according to a number of the virtual micro areas.