Semiconductor Defect Inspection Using Pattern Correlation
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Solution Overview
Problem
Current defect inspection methods in semiconductor manufacturing, such as using SEM images and CAD design data, face challenges in accurately identifying defective portions due to discrepancies caused by exposure conditions and limited image acquisition areas, leading to inefficiencies and potential misidentification of non-defective areas.
Innovation Solution
A defect inspection apparatus and method that includes a processing unit to acquire pattern data from a wafer, generate design information, assign numbers to patterns, and verify crucial defects by correlating these numbers to determine if patterns constitute a defect, thereby reducing inspection time by focusing on critical defect identification.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If Die To Database method is used to find defects by comparing SEM images with CAD design patterns, then defect detection capability is improved, but measurement precision deteriorates due to exposure condition variations causing pattern mismatches
Solution Approach 1:
The patent changes the reference parameter from ideal CAD design patterns to actual SEM images of known good wafers. By using real SEM images that already incorporate exposure condition variations as the reference, the comparison becomes more accurate and reduces false defect detections caused by normal process variations.
2Reliability
If the entire chip is verified to mitigate wiring connection issues in areas not included in SEM images, then defect detection reliability is improved, but inspection time increases significantly
Solution Approach 1:
The patent extracts and focuses inspection efforts only on specific areas where defects are actually detected in the SEM image, rather than verifying the entire chip. By taking out only the relevant regions for detailed analysis, the inspection time is significantly reduced while maintaining reliability for critical defect detection.
3Productivity
If SEM image acquisition area is limited to reduce inspection time, then productivity is improved, but measurement precision deteriorates due to inability to detect wiring connection issues in excluded areas
Solution Approach 1:
The patent uses correlation information from CAD design data as an intermediary to guide the inspection process. The CAD data provides wiring connection information that helps interpret SEM image findings, allowing the system to make informed decisions about which areas require detailed inspection and how to evaluate potential defects based on circuit connectivity.
Data Source
AI summary
An apparatus for inspecting a defect includes a memory storage and a processing unit coupled to the memory storage. The processing unit is configured to acquire pattern data for one or more patterns implemented on a wafer from a storage device, clip a portion that corresponds to the pattern data from a figure indicated by design data to generate design information and one or more circuit patterns, assign a first set of numbers to the one or more patterns of the pattern data, assign a second set of numbers to the one or more circuit patterns of the design information, generate relation information indicative of one or more correspondences between the first set of numbers and the second set of numbers, verify whether or not the one or more patterns indicated by the pattern data constitute a crucial defect based on the relation information, and send a verification result to a device.