Semiconductor Defect Prediction Using Mask Layout Risk Analysis
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Solution Overview
Problem
Current methods for detecting semiconductor physical defects, such as physical failure analysis (PFA) using transmission electron microscopes, are time-consuming and costly, and fail to efficiently identify the location of defects in semiconductor circuits.
Innovation Solution
A module comprising a defect diagnosis unit, information acquisition unit, feature classification unit, and failure risk assessment unit is used to predict semiconductor physical defects by performing defect diagnosis, feature classification, and failure risk analysis on cutting images of semiconductor mask layouts, utilizing ATPG systems and deep learning to identify high-risk positions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If physical failure analysis (PFA) using transmission electron microscope is used to verify the location of physical defect, then the location of defect can be identified, but the detection process becomes time-consuming and cost-intensive
Solution Approach 1:
The patent performs preliminary defect prediction and high-risk position identification using ATPG system and deep learning analysis on mask layout data before actual manufacturing and testing. By predicting potential defect locations in advance, the system reduces the need for extensive post-manufacturing PFA testing, thereby identifying defects earlier and reducing detection time while maintaining accurate location identification capability
Solution Approach 2:
The patent creates a virtual model of the semiconductor circuit structure by generating failure path configuration diagrams from mask layout data. This digital copy allows for simulated defect analysis and prediction without requiring physical samples, enabling early defect identification at design stage and reducing the need for time-consuming physical PFA testing on actual chips
2Measurement precision
If physical failure analysis (PFA) using transmission electron microscope is used to verify the location of physical defect, then the location of defect can be identified, but the detection cost increases
Solution Approach 1:
The patent performs preliminary defect prediction using ATPG system and deep learning analysis on mask layout data before manufacturing. By identifying high-risk positions in advance through computational methods, the system reduces the number of expensive PFA tests needed on physical samples, thereby maintaining accurate defect location identification while significantly reducing detection costs
Solution Approach 2:
The patent uses digital copies of mask layout data to generate failure path configuration diagrams and perform virtual defect analysis. This eliminates the need for expensive physical PFA testing on actual semiconductor chips, reducing detection costs while maintaining the ability to accurately identify defect locations through computational prediction
3Reliability
If scan test is performed on semiconductor chips to detect physical defects, then defects can be detected, but the scan chain circuit length and number of circuit levels are quite large making it difficult to resolve the location
Solution Approach 1:
The patent segments the complex scan chain circuit into multiple smaller segments by dividing the circuit structure into different portions and generating separate failure path configuration diagrams for each segment. This segmentation reduces the complexity of analyzing long scan chains, making it easier to identify specific defect locations while maintaining comprehensive defect detection capability across the entire circuit
Solution Approach 2:
The patent introduces failure path configuration diagrams as an intermediary representation between the physical circuit structure and the defect analysis process. These diagrams provide a simplified visual model that bridges the complexity of the scan chain circuit and the defect detection algorithm, making it easier to trace and identify defect locations without dealing directly with the full complexity of the original circuit
Data Source
AI summary
A module for predicting semiconductor physical defects includes a defect diagnosis unit used to detect at least one failure circuit in a semiconductor circuit structure; an information acquisition unit used for obtaining a semiconductor mask layout for forming the semiconductor circuit structure, and obtaining a failure path configuration diagram corresponding to the failure circuits and the location information corresponding to the failure path configuration diagram; a feature classification unit used for extracting a plurality of cutting images of the failure path configuration diagram, and performing feature classification on these cutting images to obtain a plurality of image groups; and a failure risk assessment unit used for performing a risk pre-assessment to select at least one high-risk group therefrom, and performing a failure risk analysis to predict at least one high failure risk position in the semiconductor mask layout according to the analysis results and the location information.