Semiconductor Degradation Measurement via Scan Chain Integration
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Solution Overview
Problem
Existing semiconductor devices face challenges in accurately measuring the degree of degradation of semiconductor circuits without increasing product area or power consumption, as separate devices like PVT sensors can reduce measurement accuracy due to physical distance and require additional area.
Innovation Solution
A semiconductor device utilizing a scan chain within a system-on-chip (SoC) to generate and analyze data patterns, determining the degree of degradation of IP blocks through scan in and scan out terminals, thereby eliminating the need for separate measuring devices and reducing errors from physical distance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a separate device such as a PVT sensor is added to measure the degree of degradation, then measurement capability is improved, but product area and power consumption increase
Solution Approach 1:
The patent merges the degradation measurement function with the existing scan chain structure by integrating a pattern generating circuit and an analyzing circuit into the scan chain. The pattern generating circuit generates test patterns that are scanned through the IP blocks, and the analyzing circuit analyzes the output patterns to determine degradation degree. This consolidation eliminates the need for separate PVT sensors, thereby maintaining measurement capability while reducing product area and power consumption.
2Measurement precision
If a separate device such as a PVT sensor is added to measure the degree of degradation, then measurement capability is improved, but power consumption increases
Solution Approach 1:
The patent merges the degradation measurement function with the existing scan chain structure by integrating a pattern generating circuit and an analyzing circuit into the scan chain. The pattern generating circuit generates test patterns that are scanned through the IP blocks, and the analyzing circuit analyzes the output patterns to determine degradation degree. This consolidation eliminates the need for separate PVT sensors, thereby maintaining measurement capability while reducing product area and power consumption.
3Adaptability or versatility
If a separate device is used to measure degradation, then measurement coverage is improved, but measurement precision deteriorates due to physical distance
Solution Approach 1:
The patent makes the scan chain multi-functional by enabling it to perform both its original function (testing and debugging) and degradation measurement. The same scan chain infrastructure is used to input test patterns and output result patterns for degradation analysis, eliminating the need for separate dedicated measurement devices. This approach ensures high measurement precision since the scan chain is physically integrated with the IP blocks, while maintaining universal applicability across different measurement scenarios.
Data Source
AI summary
A semiconductor device includes a processing block which comprises one or more intellectual property (IP) blocks; a scan chain which is electrically connected to the IP blocks, wherein the scan chain block has a scan in (SI) terminal and a scan out (SO) terminal; a pattern generating circuit which generates a data pattern having a plurality of bits and inputs the data pattern to the scan in (SI) terminal of the scan chain; and an analyzing circuit which determines the degree of degradation of each of the IP blocks based on a result pattern output from the scan out (SO) terminal of the scan chain.