Semiconductor Delay Circuit Layout Optimization
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in reducing chip size due to the large area occupied by delay circuits, primarily because of the space required for resistance elements and contacts, which limits area reduction and increases chip size.
Innovation Solution
The proposed solution involves optimizing the layout of delay circuits by sharing substrate and well-contacts between adjacent layout regions, allowing the resistance elements to be positioned outside the contact areas, thereby reducing the overall area occupied by the delay circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If delay circuits include resistance elements and contacts within standard cells, then the delay function is provided, but the chip area increases
Solution Approach 1:
The patent merges the delay circuit functionality with the standard cell structure by integrating the resistance element and capacitor within the standard cell boundaries. The resistance element is positioned to share contact areas with adjacent standard cells, combining multiple functions (delay + substrate contact + well contact) into a single standardized unit, thereby reducing overall chip area while maintaining the delay function.
Solution Approach 2:
The standard cell is designed to serve multiple functions: providing the delay function through the RC circuit, supplying substrate contacts for n-channel transistors, and supplying well contacts for p-channel transistors. This multi-functionality eliminates the need for separate dedicated contact areas, reducing the total area required for delay circuits.
2Stability of the object's composition
If resistance elements are surrounded by sub-contacts and well-contacts, then transistor stability is ensured, but the space occupied by delay circuits increases
Solution Approach 1:
The patent combines the contact requirements for multiple transistors into shared contact areas. The sub-contact and well-contact areas are positioned to serve both the delay circuit's resistance element and adjacent standard cells, ensuring transistor stability through proper contact while minimizing the total space occupied by eliminating redundant contacts.
3Reliability
If standard cells are designed with fixed contact areas, then reliability is maintained across various combinations, but area reduction is limited
Solution Approach 1:
The standard cell contact areas are designed to be universal, serving multiple purposes: providing substrate contacts for n-channel transistors, well contacts for p-channel transistors, and contacts for resistance elements in delay circuits. This universal design maintains reliability across various standard cell combinations while enabling area reduction through shared contact infrastructure.
Solution Approach 2:
The patent optimizes the spatial arrangement of contact areas within the standard cell, positioning them to serve multiple functions simultaneously. By carefully designing the two-dimensional layout of contact areas, the patent ensures that each contact area can serve different transistor types and delay circuit requirements, maintaining reliability while reducing the overall cell area.
Data Source
AI summary
Apparatuses including circuit layout regions of a semiconductor device and methods of designing the circuit layout regions of a semiconductor device are described. An example apparatus includes a first layout region including a first transistor area including at least one first transistor, at least one contact in proximity to the first transistor area, and a first resistor area comprising at least one first resistor coupled to the at least one first transistor. The first transistor area and the at least one contact are aligned in a first direction, and the first transistor area and the first resistor area are aligned in a second direction. The second direction may be substantially perpendicular to the first direction. The at least one contact may be one of a substrate contact and a well contact.