Semiconductor Delay Circuit for Dynamic Pre-Charge Timing Control
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Solution Overview
Problem
Semiconductor memory devices face inefficiencies in performing write, read, and pre-charge operations due to the lack of effective timing control mechanisms, leading to suboptimal operation speeds and increased latency.
Innovation Solution
Incorporating a delay circuit and column signal generation circuit that synchronize write and read signals with clock signals, generating pulses for write, read, and pre-charge operations, and using write latency and burst operation information to delay signals, ensuring efficient selection of memory cells across multiple banks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If pre-charge operation is performed after every write operation, then memory stability is improved, but operation speed deteriorates due to increased latency
Solution Approach 1:
The patent implements dynamic pre-charge timing control where the pre-charge operation is selectively performed based on whether the next operation targets the same bank. The delay circuit adjusts the pre-charge signal timing dynamically: when the next operation is on a different bank, pre-charge is performed; when it's on the same bank, pre-charge is skipped. This dynamic adaptation resolves the contradiction by maintaining memory stability only when necessary while maximizing operation speed when continuous access to the same bank is possible.
Solution Approach 2:
The patent changes the timing parameter of the pre-charge operation based on operation patterns. The delay circuit modifies the pre-charge signal delay time according to write latency information and burst operation information, allowing the system to optimize between performing pre-charge (for stability) and skipping it (for speed) based on the specific operational context and timing parameters.
2Reliability
If write latency time is increased to ensure proper data storage, then data integrity is improved, but operation efficiency deteriorates
Solution Approach 1:
The delay circuit performs preliminary timing adjustments by delaying the pre-charge signal by a calculated amount (write latency time + burst operation time) to ensure data is fully stored before pre-charge begins. This preliminary action guarantees data integrity while minimizing the actual pre-charge duration, thus maintaining operation efficiency.
Solution Approach 2:
The patent enables continuous write and read operations on the same bank by eliminating unnecessary intermediate pre-charge operations. The delay circuit maintains continuous operation flow by adjusting timing parameters to ensure proper data storage only when needed, while allowing uninterrupted access sequences to proceed without idle pre-charge cycles, thereby improving overall operation efficiency.
3Device complexity
If timing control is simplified for easier implementation, then device complexity is reduced, but timing precision deteriorates
Solution Approach 1:
The delay circuit serves as an intermediary component that handles the complex timing calculations and signal delays. By introducing this dedicated delay control unit, the patent achieves precise timing control (write latency time + burst operation time delays) without significantly increasing overall device complexity, as the delay function is encapsulated in a single modular circuit block that interfaces with existing memory and control circuits.
Data Source
AI summary
A semiconductor device includes a delay circuit and a column signal generation circuit. The delay circuit delays a write signal by a sum of a write latency time and a burst operation time to generate a write pulse, delays a read signal to generate a read pulse, and generates a pre-charge signal which is enabled after a predetermined period elapses from a time when the write signal is generated. The column signal generation circuit generates a column signal from a chip selection signal and a command/address signal when the write pulse or the read pulse is inputted to the column signal generation circuit. The column signal is a signal for selecting at least one memory cell included in one of a plurality of banks.