Semiconductor Device Delay Circuit Power Supply Voltage Control
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Solution Overview
Problem
In SRAM semiconductor devices, the operational speed is limited by the difference in power-supply voltages between the main circuit and the peripheral circuit, leading to inefficiencies in access time and power consumption, especially when a hold buffer is used.
Innovation Solution
A semiconductor device design that includes a main circuit with a memory cell array and a peripheral circuit, where the power-supply voltage for the memory cell array and sense amplifier is higher than for the delay circuit and peripheral circuit, allowing for adjustable operational speed through a second output holding circuit activated later than the first output holding circuit, utilizing a delay circuit with load capacitance to manage signal delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a hold buffer is used to synchronize signals between main circuit and peripheral circuit, then signal timing is synchronized, but operational speed is limited and access time increases
Solution Approach 1:
The patent applies dynamics by making the buffer circuit selectively activatable rather than always active. The buffer is enabled only when voltage levels differ between main circuit and peripheral circuit, allowing high-speed operation when voltages match while providing synchronization when needed. This dynamic activation resolves the contradiction between always maintaining synchronization and allowing high-speed operation.
Solution Approach 2:
The patent changes the operational parameters of the buffer circuit by controlling its activation state based on voltage level relationships. By monitoring whether VDDC (main circuit voltage) equals VDDP (peripheral circuit voltage) and selectively enabling/disabling the buffer accordingly, the system adapts its behavior to resolve the speed-synchronization contradiction.
2Use of energy by moving object
If power-supply voltage of main circuit is higher than peripheral circuit to control voltage and clock frequency, then power consumption is reduced, but operational speed becomes limited by the peripheral circuit
Solution Approach 1:
The system dynamically adjusts its operational mode based on the relationship between VDDC and VDDP. When voltages are equal, the system operates in high-speed mode without buffer intervention. When voltages differ, the buffer is activated to enable voltage-level adaptation while maintaining acceptable performance. This dynamic approach resolves the contradiction between power-saving voltage control and speed maintenance.
Solution Approach 2:
The buffer circuit acts as an intermediary between the main circuit operating at VDDC and the peripheral circuit operating at VDDP. When voltage levels mismatch, the buffer mediates the signal transfer, allowing the main circuit to operate at its optimal voltage for power efficiency while the peripheral circuit operates at its appropriate voltage level, with the buffer bridging the gap.
3Speed
If same power-supply voltage is applied to main circuit and peripheral circuit for high-speed operation, then operational speed is improved, but synchronization between circuits becomes difficult
Solution Approach 1:
The system employs dynamic buffer activation based on voltage level detection. Even when VDDC equals VDDP during high-speed operation, the system maintains the capability to activate the buffer when synchronization issues arise or when voltage levels diverge, providing adaptive synchronization support without continuously limiting speed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design allows for adjustable operational speed based on the power-supply voltage levels, reducing power consumption and shortening the active period of the word line, while maintaining high-speed operations by optimizing the timing of data output and signal activation.
Implementation Method 1
The delay circuit includes an element applying a load capacitance to a wiring of a delay signal
Data Source
AI summary
A semiconductor device includes a main circuit and a peripheral circuit inputting/outputting a signal from/to the main circuit, the main circuit including: a memory cell array; a sense amplifier; a first output holding circuit holding the read data output from the sense amplifier; a second output holding circuit receiving the read data as its input output from the first output holding circuit; and a delay circuit outputting a delay signal for activating the second output holding circuit to be later than the first output holding circuit. The delay circuit includes an element applying a load capacitance to a wiring of the delay signal. A power-supply voltage being a first voltage is supplied to the memory cell array, the sense amplifier and the first output holding circuit. A power-supply voltage being a second voltage is supplied to the delay circuit, the second output holding circuit and the peripheral circuit.