Semiconductor Read Write Leveling via Temperature-Adaptive Delay
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor devices face challenges in maintaining optimal signal timing for reading and writing operations across varying temperatures, leading to longer write recovery time and address access time due to temperature-dependent delays in control signal synchronization.
Innovation Solution
Incorporating a temperature sensor circuit and delay code generation circuit in semiconductor chips to adjust delay codes based on temperature levels, allowing for optimal timing adjustments in both high-temperature and low-temperature operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a fixed delay adjustment circuit is used to synchronize control signals, then timing margin is secured at extreme temperatures, but write recovery time and address access time increase at normal temperatures
Solution Approach 1:
The patent applies dynamics by making the delay adjustment amount variable based on temperature. The delay adjustment circuit changes its delay amount according to temperature conditions (first delay amount at first temperature condition, second delay amount at second temperature condition), allowing the system to adapt to different thermal environments rather than using a fixed delay value. This resolves the contradiction by optimizing timing margin at extreme temperatures while minimizing delay at normal temperatures.
Solution Approach 2:
The patent changes the delay parameter based on temperature conditions. The delay adjustment circuit modifies its delay amount as a parameter in response to temperature variations, selecting between different delay amounts (first delay amount vs. second delay amount) depending on whether the temperature meets the first temperature condition. This parameter change enables the system to maintain reliability at extreme temperatures while reducing time loss at normal operating conditions.
2Reliability
If delay adjustment amount is increased to ensure synchronization at low temperatures, then timing margin is improved, but address access time increases at high temperatures
Solution Approach 1:
The delay adjustment circuit dynamically adapts its delay amount based on temperature conditions. At low temperatures where synchronization is difficult, it applies a larger first delay amount to ensure proper timing margin. At high temperatures where synchronization is easier, it reduces the delay to a smaller second delay amount, thereby maintaining reliability while minimizing address access time degradation.
Solution Approach 2:
The system changes the delay parameter according to temperature conditions. The delay adjustment circuit selects between a first delay amount (for low temperature synchronization) and a second delay amount (for high temperature performance), optimizing the balance between synchronization reliability and address access time based on ambient thermal conditions.
3Speed
If separate chips are used for interface section and memory core, then transistor speed is improved, but device complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the semiconductor device into separate chips: an interface chip containing the interface section and at least one memory chip containing the memory core. This physical separation allows each chip to be optimized independently - the interface chip can use faster transistors for high-speed data processing while the memory chip focuses on storage capacity, thereby achieving speed improvement despite increased device complexity.
Data Source
AI summary
Disclosed herein is an apparatus that includes a first semiconductor chip including a first electrode, and a second semiconductor chip including a second electrode connected to the first electrode. One of the first and second semiconductor chips includes a first temperature sensor circuit generating a first detection signal, the first detection signal taking a first level when a temperature is equal to or higher than a first temperature, the first detection signal taking a second level when the temperature is lower than the first temperature; and a first delay code generation circuit outputting a first delay code signal in response to the first level of the first detection signal, and outputting a second delay code signal different from the first delay code signal in response to the second level of the first detection signal.