Semiconductor Density Mismatch Reduction via Dummy Patterns
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Solution Overview
Problem
The difference in pattern density between high and low pattern density areas in semiconductor devices leads to uneven polish rates during the formation of shallow trench isolations, resulting in step height discrepancies that affect transistor length, impedance, and gate shape, causing misalignment and shape issues in subsequent lithographic processes.
Innovation Solution
The use of dummy material is introduced in low pattern density regions to reduce density mismatches, either internally within high pattern density areas or between them, to bring conductor and active area densities closer to those of high pattern density regions, thereby stabilizing step heights and improving lithographic alignments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If chemical mechanical polish is performed on shallow trench isolations in high pattern density areas, then the isolation structures are formed, but the polish rate becomes slower causing positive step height and misalignment
Solution Approach 1:
The patent applies preliminary action by adding dummy patterns to low density areas before the chemical mechanical polish step. This pre-compensation equalizes the pattern density across different regions, ensuring that the polish rate will be uniform when the actual processing occurs, thereby preventing positive step height and maintaining lithographic alignment precision
2Manufacturing precision
If chemical mechanical polish is performed on shallow trench isolations in low pattern density areas, then the isolation structures are formed, but the polish rate becomes faster causing negative step height and gate shape distortion
Solution Approach 1:
The patent applies preliminary action by adding dummy patterns to low density areas before the chemical mechanical polish step. This pre-compensation equalizes the pattern density across different regions, ensuring that the polish rate will be uniform when the actual processing occurs, thereby preventing negative step height and maintaining gate shape integrity
3Manufacturing precision
If dummy material is added to low pattern density regions, then density mismatch is reduced and polish rate uniformity is improved, but device complexity increases
Solution Approach 1:
The patent applies local quality by adding dummy patterns only in specific low density regions where needed, rather than uniformly across the entire device. This targeted approach equalizes pattern density locally in problem areas while maintaining the original design in functional regions, thus improving polish rate uniformity without unnecessarily increasing overall device complexity
Data Source
AI summary
A system and method for reducing density mismatch is disclosed. An embodiment comprises determining a conductor density and an active area density in a high density area and a low density area of a semiconductor device. Dummy material may be added to the low density area in order to raise the conductor density and the active area density, thereby reducing the internal density mismatches between the high density area and the low density area. Additionally, a similar process may be used to reduce external mismatches between different regions on the semiconductor substrate. Once these mismatches have been reduced, empty regions surrounding the different regions may additionally be filled in order to reduce the conductor density mismatch and the active area density mismatches.