Semiconductor Deposition Feedback Control for Wafer Consistency

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Solution Overview

Problem

Challenges arise during the scaling-down process of semiconductor devices in achieving improved quality, yield, performance, and reliability while reducing complexity, particularly in the fabrication processes.

Innovation Solution

A fabrication system incorporating an artificial intelligence module that analyzes data from measurement modules to update etching, deposition, and implantation recipes in real-time, ensuring parameters are within predetermined ranges, thereby improving wafer-to-wafer consistency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Power

If semiconductor device dimensions are scaled down to improve computing ability, then device performance is improved, but manufacturing precision and process control become more difficult

Engineering Contradiction:
Improvedevice performanceVSAvoidprocess control
Core Design Contradiction:
PowerVSManufacturing precision

Solution Approach 1:

The patent implements a feedback control system where measurement modules continuously monitor wafer parameters after processing, and an AI module analyzes this data to automatically adjust process recipes for subsequent wafers. This closed-loop feedback mechanism compensates for variability introduced by scaling down device dimensions, maintaining manufacturing precision despite smaller feature sizes.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The system dynamically changes process parameters (temperature, pressure, gas flow rates, power) based on real-time measurement data and AI analysis. When deviations are detected in wafer properties, the AI module automatically adjusts recipe parameters to compensate, enabling precise control even as device dimensions scale down to more challenging sizes.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If process recipes are updated in real-time based on measurement data, then yield and reliability are improved, but system complexity increases

Engineering Contradiction:
Improvewafer yieldVSAvoidsystem complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The fabrication system performs self-correction through automated AI-based recipe updates. The system monitors its own output, analyzes deviations, and automatically adjusts process parameters without external intervention. This self-service capability improves yield while the modular integration keeps complexity manageable by eliminating manual adjustment steps.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The AI module serves multiple functions: it analyzes measurement data, determines whether adjustments are needed, generates updated recipes, and controls the implementation of new parameters. This multi-functionality consolidates what would otherwise require separate systems, improving reliability while containing overall system complexity through functional integration.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS12421595B2Deposition system for fabricating semiconductor device structure
Publication Date: 2025.09.23 NAN YA TECH
  • US12421595B2 patent drawing
  • US12421595B2 patent drawing
  • US12421595B2 patent drawing

AI summary

The present application provides a deposition system. The deposition system includes a deposition module executing a first deposition recipe on a first wafer to turn a first wafer state of the first wafer to a second wafer state; a first measurement module collecting the second wafer state of the first wafer to generate a first set of data; and an artificial intelligence module coupled to the first measurement module and the etch module, analyzing the first set of data and update the first deposition recipe to a second deposition recipe when the first set of data is not within a predetermined range. The artificial intelligence module is configured for generating the second deposition recipe taking into consideration at least one of a deposition rate of the second wafer, a rate of rotation of the second wafer, and a tilt angle of the second wafer.