Semiconductor Design Support Device Latency Analysis
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Solution Overview
Problem
Current design methods for semiconductor integrated circuits struggle to effectively manage latency in behavioral descriptions, particularly in recognizing clock cycles and synchronism, leading to inefficiencies in circuit design and increased time to market due to the complexity and size of LSI circuits.
Innovation Solution
A semiconductor design support device and method that includes a behavioral description, an RTL description, and a latency analyzer, which generates an RTL description from a behavioral description and performs logic simulations to calculate latency in each block, allowing for targeted optimization of clock cycles and synchronism.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If behavioral description is used to describe hardware processing algorithm in motion level, then design abstraction level is increased, but latency calculation and clock cycle recognition become difficult
Solution Approach 1:
The patent introduces an RTL description as an intermediary between the behavioral description and the hardware implementation. The behavioral description is synthesized into an RTL description that explicitly includes clock cycle information and synchronism concepts, which then serves as the basis for accurate latency calculation. This intermediary layer resolves the contradiction by maintaining high-level abstraction while enabling precise timing analysis.
Solution Approach 2:
The patent performs preliminary synthesis of the behavioral description into an RTL description that incorporates clock cycle information before conducting latency analysis. By preparing the RTL description in advance with explicit timing information, the system enables accurate latency calculation without requiring complex analysis of the high-level behavioral description directly.
2Measurement precision
If RTL simulation is performed to calculate latency, then latency can be determined, but design time increases
Solution Approach 1:
The patent extracts latency information directly from the RTL description through automated analysis rather than performing complete RTL simulations. By taking out only the necessary timing information from the synthesized RTL description and analyzing it selectively, the system achieves accurate latency measurement without the time-consuming overhead of full simulations.
Solution Approach 2:
The patent creates a simplified copy or representation of the timing behavior from the RTL description that can be analyzed independently. Instead of running full simulations, the system generates and analyzes a timing model or representation derived from the RTL description, achieving the same measurement accuracy with reduced computational time.
3Productivity
If behavioral description is analyzed to find high-latency blocks, then optimization can be targeted, but analysis effectiveness is insufficient with known methods
Solution Approach 1:
The patent uses the RTL description as an intermediary to enable effective analysis of behavioral description blocks. The RTL description maintains the structural correspondence with the behavioral description while adding explicit timing information, allowing accurate identification of high-latency blocks through analysis of the RTL representation rather than the behavioral description directly.
Solution Approach 2:
The patent enhances the visibility of timing information by representing latency data in the RTL description with distinct markers or annotations (analogous to color changes). This makes high-latency blocks easily identifiable through automated analysis tools that can detect and highlight blocks with excessive latency requirements, improving analysis effectiveness.
Data Source
AI summary
A semiconductor design support device for designing a semiconductor integrated circuit includes a behavioral description, an RTL description, and a latency analyzer. The behavioral description describes an algorithm of processing performed by hardware in a motion level. The RTL description is generated by reading the behavioral description and recognizes a concept including register and clock synchronism peculiar to the hardware. The latency analyzer analyzes a result of a logic simulation performed on the RTL description to calculate a latency in each block representing an operation in a predetermined unit in the behavioral description.