Semiconductor Design Parameter Segmentation for Performance Matching
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional semiconductor device design uses a single interconnect structure for each generation, leading to mismatched transistor and interconnect parameters, resulting in insufficient performance across high-performance MPU and low-power-consumption LSI devices in terms of operation speed, power consumption, chip size, and reliability.
Innovation Solution
A method is introduced to design semiconductor devices by setting multiple suites of device parameters that match transistor and interconnect characteristics for a single CMOS generation, allowing for the selection of parameters tailored to specific performance requirements, thereby avoiding mismatches and optimizing performance across different applications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single interconnect structure is used for each generation, then device complexity is reduced, but performance matching between transistor and interconnect deteriorates
Solution Approach 1:
The patent segments the interconnect structure into multiple types (first type with higher resistance and second type with lower resistance) that can be selectively applied to different transistor types. This segmentation allows high-performance transistors to be paired with low-resistance interconnects for speed-critical applications, while low-power transistors are paired with high-resistance interconnects for power-critical applications, thereby resolving the performance matching issue without requiring complete redesign of the entire interconnect system.
Solution Approach 2:
The patent applies local quality by assigning different interconnect characteristics to different regions or applications within the same device. Specifically, low-resistance interconnects are used in regions where high-performance transistors are placed, while high-resistance interconnects are used in regions with low-power transistors. This localized optimization ensures that each transistor-interconnect pair is matched according to its specific performance requirements.
2Speed
If interconnect structure is optimized for high-performance MPU, then operation speed is improved, but power consumption increases
Solution Approach 1:
The patent changes the resistance parameter of the interconnect structure by providing multiple interconnect types with different resistance characteristics. Low-resistance interconnects are used when high operation speed is required for high-performance MPU, while high-resistance interconnects are used when low power consumption is required for low-power LSI. This parameter change allows the same transistor type to achieve different performance outcomes based on the interconnect selection.
3Use of energy by moving object
If interconnect structure is optimized for low-power LSI, then power consumption is reduced, but operation speed deteriorates
Solution Approach 1:
The patent applies parameter changes by selecting interconnects with higher resistance for low-power LSI applications. The higher resistance reduces current flow and thereby reduces power consumption, while still maintaining adequate operation speed for power-critical applications. This parameter selection allows the system to prioritize power efficiency over maximum speed when appropriate.
4Adaptability or versatility
If multiple suites of device parameters are provided, then performance adaptability is improved, but device complexity increases
Solution Approach 1:
The patent segments the parameter specifications into multiple suites, where each suite contains coordinated transistor and interconnect parameters optimized for specific applications. The first suite optimizes for high performance with low-resistance interconnects, while the second suite optimizes for low power consumption with high-resistance interconnects. This segmentation of parameters allows flexible selection based on application requirements without requiring complete redesign of the device.
Data Source
AI summary
Aiming at providing a method of designing a semiconductor device capable of producing a semiconductor device which expresses performances adapted to required performances, the present invention sets a plurality of suites of device parameters, containing parameters relevant to transistor characteristics (transistor parameters) and parameters relevant to interconnect characteristics (interconnect parameters) corresponded to the transistor characteristics, for a single CMOS generation, selecting, out of the plurality of suites, a suite matched to performances required for a semiconductor to be designed, and designing the semiconductor device.