Semiconductor Detector Electrode Structure for Low-Noise SEM Sensing
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Solution Overview
Problem
Current semiconductor radiation detectors in SEM systems face limitations in sensitivity and speed due to high series resistance and noise, which affect the accuracy and yield of IC component inspections as feature sizes shrink, especially when operating at low beam currents and high throughput.
Innovation Solution
The implementation of a semiconductor detector with a buried portion in the top electrode and an isolation structure near the sidewalls of the hole, combined with high-temperature pure boron chemical vapor deposition (HT PureB CVD) for CMOS circuitry, reduces series resistance and noise, enhancing detection efficiency and bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a conventional top electrode structure is used, then the manufacturing process is simple, but the series resistance is high which reduces detection speed
Solution Approach 1:
The patent introduces a buried portion of the top electrode extending beneath the detecting layer into the semiconductor structure, transitioning from a purely surface-level electrode to a three-dimensional structure that spans multiple layers. This dimensional extension reduces series resistance by providing additional conduction pathways without increasing the surface footprint, thereby improving detection speed while maintaining compact form factor.
2Reliability
If the active area is increased to improve sensitivity, then more electrons can be detected, but the series resistance increases which reduces speed
Solution Approach 1:
The buried electrode portion extends vertically beneath the detecting layer, creating a three-dimensional conduction network. This allows the surface active area to be maximized for sensitivity while the subsurface electrode structure provides low-resistance pathways that prevent speed degradation, effectively decoupling the sensitivity-speed tradeoff.
3Speed
If high temperature processing is used to reduce series resistance, then detection speed improves, but existing CMOS circuitry is damaged
Solution Approach 1:
The patent segments the fabrication process into distinct temperature zones: early stages use low-temperature processing compatible with CMOS circuitry to form initial structures, while later stages apply high-temperature processing only to specific regions (such as forming the buried electrode portion) after heat-sensitive circuitry is already in place or protected. This temporal and spatial segmentation allows both low-temperature circuit fabrication and high-temperature resistance reduction.
Solution Approach 2:
The patent performs preliminary fabrication of CMOS circuitry at low temperatures before applying high-temperature processing for series resistance reduction. By establishing the circuitry first and then applying targeted high-temperature steps, the patent ensures circuit integrity while achieving the desired electrical performance improvements in the detector elements.
4Measurement precision
If isolation structures are added near sidewalls to reduce noise, then detection accuracy improves, but manufacturing complexity increases
Solution Approach 1:
The patent combines the isolation structure formation with the electrode structure fabrication by integrating the buried electrode portion with the isolation regions near the sidewalls. This merging of functions reduces the number of separate fabrication steps and materials required, achieving noise reduction through a unified structure rather than adding separate isolation components.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves the sensitivity and speed of semiconductor detectors, maintaining high quantum efficiency and reducing noise, enabling better accuracy and yield in IC component inspections, even at low beam currents and high throughput.
Implementation Method 1
the buried portion is configured to reduce a series resistance of the top electrode
Implementation Method 2
applying a thermal treatment to drive dopants from the dopant layer into the semiconductor structure and underneath a detecting layer of the top electrode
Implementation Method 3
high-temperature pure boron chemical vapor deposition (HT PureB CVD)
Data Source
AI summary
The present disclosure describes a detector used in critical dimension scanning electron microscopes (CD-SEM) and review SEM systems. In one embodiment, the detector includes a semiconductor structure having a p-n junction and a hole through which a scanning beam is passed to a target. The detector also includes a top electrode for the p-n junction (e.g., anode or cathode) that provides an active area for detecting electrons or electromagnetic radiation (e.g., backscattering from the target). The top electrode has a doped layer and can also have a buried portion beneath the doped layer to reduce a series resistance of the top electrode without changing the active area. In another embodiment, an isolation structure can be formed in the semiconductor structure near sidewalls of the hole to electrically isolate the active area from the sidewalls. A method for forming the buried portion of the top electrode is also described.