Semiconductor Device Parasitic Capacitance Reduction
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Solution Overview
Problem
Parasitic capacitance issues arise in semiconductor devices where bonded semiconductor chip sections exhibit pair ground capacitance and adjacent coupling capacitance, affecting performance and interfering with signal processing in solid-state imaging devices.
Innovation Solution
A semiconductor device configuration where the first and second semiconductor sections are secured with their respective wiring layers facing each other, and a conductive material extends through the first section to the second section for electrical communication, with options for plasma bonding or adhesive securing, and a control region between the pixel array and removal region to reduce parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If semiconductor chip sections are bonded together with wiring layers facing each other to reduce parasitic capacitance, then signal processing performance is improved, but manufacturing complexity increases due to precise alignment requirements
Solution Approach 1:
The patent applies preliminary action by pre-forming protrusions on one wiring layer and corresponding recesses on the opposing wiring layer before bonding. This preliminary structuring enables self-alignment during the bonding process, reducing the need for complex post-bonding adjustments and simplifying manufacturing while maintaining the wiring layers' facing configuration for parasitic capacitance reduction
2Reliability
If a conductive material is extended through the first semiconductor section to connect wiring layers, then electrical communication is achieved, but parasitic capacitance increases due to additional conductive paths
Solution Approach 1:
The patent extracts the harmful semiconductor material from the region where the conductive connection is needed by forming a removal region. This allows the conductive material to be placed directly on the substrate without the underlying semiconductor material, thereby achieving electrical communication between wiring layers while eliminating the parasitic capacitance that would otherwise be generated by conductive paths through the semiconductor section
3Strength
If plasma bonding is used to secure semiconductor sections, then bonding strength is improved, but manufacturing process complexity increases
Solution Approach 1:
The patent introduces an adhesive layer as an intermediary between the semiconductor chip sections, replacing direct plasma bonding. This adhesive mediator achieves sufficient bonding strength while simplifying the manufacturing process, as adhesive bonding is a more straightforward and controllable process compared to plasma bonding, thereby reducing manufacturing process complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces parasitic capacitance, enhancing the performance of solid-state imaging devices by improving signal processing and reducing interference, leading to high-performance semiconductor devices and electronic apparatuses like cameras.
Implementation Method 1
a conductive material extending through the first semiconductor section to the second wiring layer of the second semiconductor section and by means of which the first and second wiring layers are in electrical communication
Implementation Method 2
the first and second semiconductor sections being secured together with the respective first and second wiring layer sides of the first and second semiconductor sections facing each other
Data Source
AI summary
A semiconductor device comprising a first semiconductor section including a first wiring layer at one side thereof, a second semiconductor section including a second wiring layer at one side thereof, the first and second semiconductor sections being secured together with the respective first and second wiring layer sides of the first and second semiconductor sections facing each other, a conductive material extending through the first semiconductor section to the second wiring layer of the second semiconductor section and by means of which the first and second wiring layers are in electrical communication.