Semiconductor Device Outer Peripheral Electrode Design
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Solution Overview
Problem
Existing semiconductor devices with superjunction structures face challenges in controlling electric characteristics to direct current flow to the outer peripheral portion when turned off, leading to longer reverse recovery times.
Innovation Solution
A semiconductor device design with a column layer connected to an outer peripheral electrode independent of the source electrode, incorporating a carrier obstructing portion with a trap level region or minute concavo-convex portions, allows current to preferentially flow to the outer peripheral portion, facilitating carrier recombination and reducing reverse recovery time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If a trap level is formed in a region directly under the column layer, then carriers are trapped and reverse recovery time is reduced, but the reverse recovery time cannot be shortened further because the trap level is not positioned where carriers are most densely distributed during turn-off
Solution Approach 1:
The patent applies local quality by forming the trap level region specifically in the outer peripheral portion of the semiconductor layer, rather than uniformly throughout. This localized approach concentrates carrier trapping capability precisely where carriers are most densely distributed during turn-off, maximizing trapping efficiency in the critical region while maintaining overall device performance.
Solution Approach 2:
The trap level region is formed in advance during the manufacturing process, before the device operates. This preliminary formation of the trap level structure ensures that when the device turns off, carriers are immediately trapped in the outer peripheral portion, reducing reverse recovery time without requiring real-time adjustment.
2Ease of operation
If the column layer is connected to the source electrode, then the device structure is simpler, but electric current cannot be directed to preferentially flow to the outer peripheral portion during turn-off
Solution Approach 1:
The patent segments the electrode connection by providing a separate outer peripheral electrode that is independent from the source electrode. The column layer is connected to this outer peripheral electrode rather than the source electrode, creating distinct current paths. This segmentation enables independent control of current flow to the outer peripheral portion, allowing preferential current direction during turn-off while maintaining manageable device complexity through modular electrode design.
3Loss of time
If the trap level region is formed in the outer peripheral portion, then carrier recombination is enhanced and reverse recovery time is shortened, but the manufacturing precision required for selective formation is increased
Solution Approach 1:
The patent introduces a mask layer as an intermediary element during the ion implantation process. This mask layer selectively blocks ion implantation in the inner portion of the semiconductor layer, allowing trap levels to be formed only in the outer peripheral portion. The mask layer simplifies the manufacturing process by providing a straightforward method to achieve selective trap level formation without requiring complex precision control, as the mask can be easily patterned and removed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively controls current flow to the outer peripheral portion, reducing reverse recovery time and improving electric characteristics during turn-off, while expanding the depletion layer and enhancing withstand voltage.
Implementation Method 1
carriers are trapped by the trap level formed below the column layer
Implementation Method 2
the column layer is subjected to heavy-particle irradiation, so that a trap level is locally formed
Implementation Method 3
expanding the depletion layer and enhancing withstand voltage
Data Source
AI summary
A semiconductor device includes a first conductivity type semiconductor layer including an active cell portion and an outer peripheral portion around the active cell portion, a second conductivity type body region selectively formed at a surface portion of the semiconductor layer in the active cell portion, a first conductivity type source region formed at an inner part of the body region, a gate electrode that faces a part of the body region through a gate insulating film, a second conductivity type column layer straddling a boundary between the active cell portion and the outer peripheral portion inside the semiconductor layer such that the column layer is disposed at a lower part of the body region in the active cell portion, a source electrode that is electrically connected to the source region, and an outer peripheral electrode that is electrically connected to the column layer in the outer peripheral portion.