Semiconductor Device Self-Aligned Contact Etching
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As semiconductor devices shrink, achieving effective separation and reducing contact resistance between conductive layers becomes increasingly challenging, particularly in the etching of interlayer dielectric layers between source/drain epitaxial layers, where there is a trade-off between etching capability and loss of metal gate cap layers and sidewall spacers.
Innovation Solution
The method involves forming a self-aligned contact process using polymers to enhance etch selectivity during dry etching, followed by wet etching with dilute HF to remove the interlayer dielectric layer without damaging the cap layers or sidewall spacers, and using a dielectric filling layer to compensate for etched materials, thereby maintaining electrical separation around metal gates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If dry etching is used to remove the interlayer dielectric layer, then etching capability is improved, but the metal gate cap layers and sidewall spacers are damaged
Solution Approach 1:
The etching process is divided into two distinct stages: first, a self-aligned contact process using polymers and dry etching to create initial openings with high etching capability; second, a wet etching process using dilute HF to complete the removal of the interlayer dielectric layer. This segmentation allows each process to be optimized for its specific function, with dry etching providing the necessary etching power and wet etching providing the necessary selectivity and gentleness.
Solution Approach 2:
Polymers are introduced as an intermediary material to enhance etch selectivity during the dry etching process. The polymers are deposited on the metal gate cap layers and sidewall spacers, creating a protective layer that allows dry etching to proceed while minimizing damage to these sensitive structures. This intermediary layer enables the use of aggressive dry etching conditions without causing harmful effects to the cap layers and spacers.
2Length of moving object
If etching capability is increased to remove interlayer dielectric in tight spaces, then separation between conductive layers is improved, but contact resistance increases due to loss of cap layers and sidewall spacers
Solution Approach 1:
A dielectric filling layer is deposited beforehand to compensate for the materials that will be etched away during the interlayer dielectric removal process. This cushioning layer ensures that even when the interlayer dielectric is completely removed to achieve tight separation between conductive layers, there remains sufficient dielectric material to maintain proper spacing and prevent short circuits, thereby maintaining low contact resistance and reliable electrical connections.
3Manufacturing precision
If wet etching with dilute HF is used, then selectivity is improved to protect cap layers and sidewall spacers, but etching capability is reduced
Solution Approach 1:
The etching process is divided into two distinct stages: first, a self-aligned contact process using polymers and dry etching to create initial openings with high etching capability; second, a wet etching process using dilute HF to complete the removal of the interlayer dielectric layer. This segmentation allows each process to be optimized for its specific function, with dry etching providing the necessary etching power and wet etching providing the necessary selectivity and gentleness.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for precise removal of the interlayer dielectric layer in tight spaces, minimizing damage to the metal gate cap layers and sidewall spacers, thereby reducing contact resistance and improving electrical isolation.
Implementation Method 1
forming a self-aligned contact process using polymers to enhance etch selectivity during dry etching
Implementation Method 2
wet etching with dilute HF to remove the interlayer dielectric layer without damaging the cap layers or sidewall spacers
Data Source
AI summary
A semiconductor device includes: an isolation insulating layer; fin structures protruding from the isolation insulating layer; gate structures, each having a metal gate and a cap insulating layer disposed over the metal gate; a first source/drain epitaxial layer and a second source/drain epitaxial layer disposed between two adjacent gate structures; and a first conductive contact disposed on the first source/drain epitaxial layer, and a second conductive contact disposed on the second source/drain epitaxial layer; a separation isolation region disposed between the first and second conductive contact; and an insulating layer disposed between the separation isolation region and the isolation insulating layer. The separation isolation region is made of a different material than the insulating layer.