Packaged Semiconductor Device With EMI Shielding Layer
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Solution Overview
Problem
Current packaging technologies for integrated circuits face challenges in achieving lower costs, higher performance, and increased density, particularly in the integration of IC die and packages, such as in package-on-package (PoP) technology, where efficient redistribution layers and conductive via formation are crucial for thinner and more complex semiconductor devices.
Innovation Solution
A method involving the formation of a polymer buffer layer, seed metal layer, and conductive via sets, followed by die bonding, encapsulation, redistribution layer formation, and conductive bump creation, with specific processes like chemical vapor deposition and photolithography, to enable efficient electrical connectivity and packaging of semiconductor devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If package-on-package technology is used to increase integration density, then device density and performance are improved, but manufacturing complexity increases
Solution Approach 1:
The patent divides the semiconductor device into multiple stacked packages (first package structure and second package structure) that can be manufactured separately and then integrated. Each package structure contains its own die, encapsulation material, and conductive elements, allowing independent fabrication before final assembly into the PoP configuration.
Solution Approach 2:
The patent implements a nested structure where one package structure is positioned and bonded onto another package structure, creating a vertical stack. The first package structure serves as the base layer, and the second package structure is nested on top, with conductive bumps from the upper package connecting to corresponding pads on the lower package, achieving three-dimensional integration.
2Length of moving object
If thinner packages are fabricated through pre-stacking or SoC integration, then package thickness is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent performs preliminary bonding and alignment of the first and second package structures during the fabrication process before final encapsulation. The carrier substrates are used to hold and position the package structures in their correct relative positions early in the process, ensuring proper alignment of conductive bumps with corresponding pads before the structures are permanently bonded together.
Solution Approach 2:
The patent uses carrier substrates as intermediary elements during the bonding process. These carriers hold the package structures and facilitate precise alignment and bonding between the first and second packages. The carriers can be removed after bonding, having served their purpose as temporary support and alignment fixtures during the critical joining operation.
3Reliability
If redistribution layers and conductive vias are integrated into thinner packages, then electrical connectivity is improved, but manufacturing process complexity increases
Solution Approach 1:
The patent combines multiple functions into integrated structures: the encapsulation material serves both as protective packaging and as a medium containing the conductive vias that provide electrical pathways. The redistribution layers are formed as part of the package structure fabrication process, integrating signal routing functions directly into the package substrate rather than requiring separate external routing layers.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the fabrication of packaged semiconductor devices with improved electrical connectivity and package density, enabling thinner and more complex designs while maintaining reliability and performance.
Implementation Method 1
a polymer buffer layer is formed on the carrier
Implementation Method 2
seed metal layer, and conductive via sets, followed by die bonding
Data Source
AI summary
In accordance with some embodiments of the present disclosure, a packaged semiconductor device includes a first package structure, at least one outer conductive bump, a second package structure, a sealing material, and an electromagnetic interference (EMI) shielding layer. The first package structure has a first cut edge. The outer conductive bump is disposed on the first package structure and has a second cut edge. The second package structure is jointed onto the first package structure. The sealing material is disposed on the first package structure, surrounds the second package structure, and covers the outer conductive bump. The sealing material has a third cut edge. The EMI shielding layer contacts the first cut edge, the second cut edge and the third cut edge. The EMI shielding layer is electrically connected with the outer conductive bump.