Semiconductor Device U-Shaped Source/Drain Epitaxial Layer
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Solution Overview
Problem
As semiconductor devices are scaled down, their operational properties deteriorate, and existing technologies face challenges in maintaining high performance and uniformity in the formation of active fins with precise sidewall profiles, leading to difficulties in achieving improved electric characteristics.
Innovation Solution
The semiconductor device incorporates a source/drain epitaxial layer with multiple epitaxial layers and an impurity diffusion region, featuring a 'U'-shaped profile, formed through selective epitaxial growth and thermal diffusion, which enhances the doping concentration gradient and improves the electrical characteristics by utilizing a 'U'-shaped junction profile.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If semiconductor devices are scaled down to reduce size and design rule, then device density increases, but operational properties deteriorate
Solution Approach 1:
The patent transitions from planar 2D FET architecture to 3D vertically-stacked FET architecture. Multiple active patterns are stacked vertically above each other, with gate structures wrapping around the active patterns in three dimensions. This vertical stacking enables higher device density while maintaining adequate channel dimensions for operational performance.
Solution Approach 2:
The gate structures are positioned to surround and enclose the active patterns, with gate electrodes wrapping around the active patterns from multiple directions. This nested configuration allows the gate to control multiple channels simultaneously, improving device performance while occupying minimal footprint area.
2Ease of manufacture
If conventional fabrication methods are used for active fin formation, then manufacturing process is simple, but sidewall profile uniformity and precision are poor
Solution Approach 1:
sacrificial patterns are formed beforehand to define the precise geometry of active fins. These sacrificial patterns serve as templates that guide subsequent self-aligned etching processes, ensuring uniform sidewall profiles are achieved before the actual active fin formation occurs.
Solution Approach 2:
Self-aligned etching processes are employed where the sacrificial patterns automatically define the etch boundaries. The etch process uses the sacrificial patterns as built-in masks, eliminating the need for additional alignment steps and ensuring precise sidewall profiles are formed without requiring complex external alignment equipment.
3Device complexity
If single-layer source/drain structure is used, then fabrication process is simple, but doping concentration gradient and electrical characteristics are insufficient
Solution Approach 1:
The source/drain structure is divided into multiple epitaxial layers with different doping concentrations. Each layer serves a specific function: the first layer provides a transition region, the second layer provides high doping concentration for ohmic contact, and the third layer provides moderate doping for channel formation. This segmentation enables precise control of electrical characteristics.
Solution Approach 2:
Different regions of the source/drain structure are assigned different doping concentrations tailored to their specific functional requirements. The region adjacent to the channel has higher doping for good contact, while regions extending into the channel have lower doping to maintain carrier mobility. This local optimization of doping quality improves overall device performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves the electric characteristics of the semiconductor device by allowing more surface areas to function as channel regions, enhancing carrier mobility and uniformity, thereby overcoming the challenges of scale-down limitations in active fin formation.
Implementation Method 1
a source/drain epitaxial layer formed in the recess
Implementation Method 2
an impurity diffusion region formed in the active pattern surrounding the source/drain epitaxial layer
Data Source
AI summary
Provided are a semiconductor device and a method of fabricating the same. The device may include an active pattern protruding from a substrate, gate structures crossing the active pattern, and a source/drain region provided between adjacent ones of the gate structures. The source/drain region may include a source/drain epitaxial layer in a recessed region, which is formed in the active pattern between the adjacent ones of the gate structures. Further, an impurity diffusion region may be provided in the active pattern to enclose the source/drain epitaxial layer along inner surfaces of the recessed region.