Semiconductor Device Etching for Power Transistor Performance

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Solution Overview

Problem

Power transistors in automotive and industrial electronics face challenges in achieving low on-state resistance while maintaining high voltage blocking capability, particularly in thin semiconductor substrates where existing methods are inefficient in manufacturing and patterning.

Innovation Solution

A method involving the formation of a mask with inert structures on a semiconductor substrate, followed by epitaxial growth and anisotropic etching, which induces different etch rates based on the pattern of inert structures, allowing for the creation of a power semiconductor device with a stepped rear surface and controlled thickness, enabling efficient voltage blocking and current conduction.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Length of stationary object

If conventional manufacturing methods are used on thin substrates, then substrate thickness is reduced, but manufacturing efficiency and patterning quality deteriorate

Engineering Contradiction:
Improvesubstrate thicknessVSAvoidmanufacturing efficiency
Core Design Contradiction:
Length of stationary objectVSProductivity

Solution Approach 1:

The method performs preliminary thinning of the substrate before device fabrication, and uses preliminary patterning steps to create masks that define subsequent etching regions. This preliminary action enables efficient processing of thin substrates without compromising manufacturing productivity.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent replaces conventional mechanical patterning methods with chemical etching processes that use patterned masks. This substitution allows for higher precision and efficiency in creating device structures on thin substrates, resolving the contradiction between substrate thinness and manufacturing efficiency.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

2Manufacturing precision

If conventional etching methods are used, then manufacturing process is simple, but etching precision and anisotropy are insufficient

Engineering Contradiction:
Improveetching precisionVSAvoidetching process complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent introduces patterned masks as intermediary structures that mediate between the etching chemistry and the desired final pattern. These masks enable precise control over etching locations and depths, achieving high etching precision while managing process complexity through systematic mask design and application.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The method applies different etching conditions and mask patterns to different regions of the substrate to achieve locally optimized etching precision. By varying mask patterns, etching times, and chemical compositions across different areas, the process achieves high precision without requiring uniformly complex procedures throughout.

Inventive Principle:
Principle #3Local quality

3Reliability

If uniform thickness is maintained, then manufacturing is easier, but on-state resistance increases

Engineering Contradiction:
Improvevoltage blocking capabilityVSAvoidsubstrate processing simplicity
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The patent creates local variations in substrate thickness through selective etching processes. Different regions of the substrate are etched to different depths based on patterned masks, creating locally optimized thickness profiles that reduce on-state resistance in current-conducting regions while maintaining adequate thickness for voltage blocking in other regions.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The substrate is segmented into different thickness zones through selective etching. By dividing the substrate into regions with different thicknesses tailored to specific functional requirements, the method simultaneously achieves low on-state resistance in active regions and high voltage blocking capability in termination regions.

Inventive Principle:
Principle #1Segmentation

4Reliability

If rear surface is left flat, then processing is simpler, but voltage blocking performance is reduced

Engineering Contradiction:
Improvevoltage blocking capabilityVSAvoidsurface structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The method performs preliminary patterning of the rear surface using etching processes before final device assembly. By creating the stepped structure in advance, the patent enables improved voltage blocking performance without complicating subsequent processing steps, as the structured surface is already in place for subsequent operations.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively reduces on-state resistance and enhances voltage blocking capability by creating a semiconductor device with a patterned rear surface and controlled thickness, improving the performance and robustness of power transistors in thin substrates.

Implementation Method 1

thereafter, anisotropically etching a semiconductor region laterally adjoining the inert structures

Methodology Applied
Scientific EffectAnisotropic etching:

Implementation Method 2

forming a semiconductor layer over the first main surface

Methodology Applied
Scientific EffectEpitaxial growth: Epitaxy

Data Source

PatentUS10497583B2Method for manufacturing a semiconductor device comprising etching a semiconductor material
Publication Date: 2019.12.03 INFINEON TECHNOLOGIES AG
  • US10497583B2 patent drawing
  • US10497583B2 patent drawing
  • US10497583B2 patent drawing

AI summary

According to embodiments, a method for manufacturing a semiconductor device includes forming a mask comprising a pattern of inert structures on a side of a first main surface of a semiconductor substrate. A semiconductor layer is formed over the first main surface, and the semiconductor substrate is thinned from a second main surface opposite to the first main surface. Thereafter, a semiconductor region laterally adjoining the inert structures is anisotropically etched.