Semiconductor Device Heat Dissipation via Recessed Circuit Pattern
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Solution Overview
Problem
Semiconductor devices face challenges in efficiently disposing IGBTs and FWDs of varying chip sizes on a limited substrate area, leading to heat concentration at the central portion, which affects rated current and device characteristics.
Innovation Solution
The semiconductor device incorporates a recessed first circuit pattern with a U-shaped design, allowing semiconductor chips to be positioned on the periphery, while the second circuit pattern is placed in the recessed area, dispersing heat and improving heat dissipation, and ensuring balanced operation by collecting output currents on the central circuit pattern.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If IGBTs and FWDs are disposed in block at the central portion of the substrate to efficiently utilize the limited substrate area, then the substrate area utilization is improved, but heat concentration occurs at the central portion affecting rated current and device characteristics
Solution Approach 1:
The substrate area is segmented into a central disposition area and a peripheral disposition area, with different semiconductor chips disposed in each region. This segmentation allows heat-generating components to be distributed across different zones rather than concentrated in one location, thereby improving heat dissipation while maintaining high substrate area utilization.
Solution Approach 2:
Different regions of the substrate are assigned different functions: the central portion is optimized for electrical connection and control, while the peripheral portion is optimized for heat dissipation. This local quality differentiation allows each region to perform its specific function effectively, resolving the conflict between area utilization and heat management.
2Ease of manufacture
If IGBTs and FWDs of different chip sizes are disposed alternately upward and downward from the central portion to optimize external terminals and connection wirings, then the wiring optimization is improved, but heat concentration at the central portion worsens
Solution Approach 1:
The disposition pattern is segmented into alternating rows of different chip types extending from the central portion. This segmentation allows wiring to be optimized in the central region while heat-generating chips are distributed in a pattern that prevents concentration, achieving both wiring optimization and heat management.
Solution Approach 2:
The disposition pattern uses asymmetric arrangement of different chip types (IGBTs and FWDs with different sizes) in alternating rows, allowing the wiring layout to be optimized for electrical performance while the asymmetric heat distribution from different chip types prevents uniform heat concentration.
Data Source
AI summary
A semiconductor device having an arm block. The arm block includes a first circuit pattern that, in a plan view of the semiconductor device, has a recess formed thereon that extends inward from a side thereof, the recess forming a disposition area of the semiconductor device, a second circuit pattern having at least a part disposed in the disposition area, and a plurality of semiconductor chips formed on the first circuit pattern. Each semiconductor chip has a positive electrode on a back surface thereof, and a control electrode and a negative electrode on a front surface thereof, the negative electrode being electrically connected to the second circuit pattern by a wiring member.