Semiconductor Device High Carrier Concentration Area On Resistance
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Solution Overview
Problem
Existing vertical transistors with trench gate structures face challenges in reducing on resistance while maintaining breakdown voltage due to the extension of the depletion layer into the current dispersion layer, which is exacerbated by increasing carrier concentration or thickness in the current dispersion layer.
Innovation Solution
A semiconductor device configuration with a high carrier concentration area located away from the trench on the substrate side, allowing current dispersion in the plane direction, reducing on resistance without compromising breakdown voltage, achieved by optimizing carrier concentration and thickness within specific ranges.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the carrier concentration or thickness of the current dispersion layer is increased to suppress the depletion layer effects, then the on resistance is reduced, but the breakdown voltage is reduced due to potential crowding at the trench corner
Solution Approach 1:
The patent applies local quality by creating a high carrier concentration area with a peak in the thickness direction at a specific location away from the trench. This localized modification of carrier concentration distribution allows current dispersion in the plane direction without causing potential crowding at the trench corner, thus reducing on resistance while maintaining breakdown voltage
Solution Approach 2:
The patent transitions from modifying the current dispersion layer (which would affect the vertical structure near the trench) to creating a high carrier concentration area in the first semiconductor layer at a location away from the trench. This spatial relocation in the plane direction allows current to disperse horizontally, avoiding the depletion layer interference zone while maintaining effective current distribution
2Loss of energy
If a current dispersion layer is provided between the drift layer and channel layer to reduce on resistance, then current dispersion is improved, but the depletion layer extends into this layer and interferes with current dispersion
Solution Approach 1:
The patent extracts the high carrier concentration area from the traditional current dispersion layer location (between drift layer and channel layer) and places it in the first semiconductor layer (drift layer) at a location away from the trench. This relocation removes the high carrier concentration region from the interference zone of the depletion layer, eliminating the harmful interaction while preserving current dispersion functionality
Solution Approach 2:
The high carrier concentration area acts as an intermediary that enables current dispersion in the plane direction without directly interacting with the depletion layer. By positioning this high carrier concentration region away from the trench in the drift layer, it serves as a mediator that facilitates current distribution while avoiding the p-n junction interface where the depletion layer forms
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The configuration effectively disperses current in the plane direction, reducing on resistance while maintaining sufficient breakdown voltage, even when using compound semiconductors like gallium nitride.
Implementation Method 1
the first semiconductor layer has a carrier concentration that provides a peak in a thickness direction perpendicular to the plane direction, and a high carrier concentration area having a peak of the carrier concentration in the first semiconductor layer is extended in the plane direction
Data Source
AI summary
There is provided a semiconductor device comprising a substrate, a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, a trench and an insulating film arranged to cover a surface of the trench. The first semiconductor layer has a carrier concentration that provides a peak in a thickness direction perpendicular to a plane direction. A high carrier concentration area having a peak of the carrier concentration in the first semiconductor layer is extended in the plane direction at a location away from the trench to be located on the substrate side of the trench. This configuration reduces the on resistance while suppressing reduction of the breakdown voltage in the semiconductor device.