Semiconductor Device With High Concentration Region Peaks
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Solution Overview
Problem
Semiconductor devices like IGBTs face challenges in achieving high withstand capability against back surface avalanche breakdown, which limits their short-circuit performance and switching speed due to the limitations in doping concentration and distribution of the collector and buffer regions.
Innovation Solution
The semiconductor device incorporates a high concentration region with specific doping concentration peaks and distribution, a collector region with controlled doping concentration, and a buffer region with strategically positioned peaks to enhance the base transport factor and prevent back surface avalanche, while maintaining low turn-off power loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the doping concentration of the collector region is increased to improve short-circuit withstand capability, then the withstand capability improves, but the turn-off power loss increases
Solution Approach 1:
The patent introduces a high concentration region with specific doping concentration peaks at predetermined positions between the drift region and collector region. This creates localized areas of high doping concentration that prevent back surface avalanche without requiring uniform high doping throughout the collector region, thus maintaining low turn-off power loss while improving short-circuit withstand capability.
Solution Approach 2:
The patent optimizes the doping concentration distribution by controlling the peak positions and concentrations in the high concentration region. By adjusting these parameters (peak position within 0.5-2.0 μm from drift region, peak concentration between 1.0×10^16 to 1.0×10^18/cm³), the device achieves improved short-circuit performance without the penalty of increased turn-off power loss that would result from uniform collector doping increases.
2Speed
If the doping concentration distribution is optimized to prevent back surface avalanche, then the switching speed improves, but the device complexity increases
Solution Approach 1:
The high concentration region is divided into multiple segments with distinct doping concentration peaks at different positions. This segmentation allows each peak to serve a specific function in preventing back surface avalanche at different locations, achieving improved switching speed while maintaining a manageable structural complexity through systematic peak placement.
3Reliability
If the integrated concentration of the high concentration region is increased to improve base transport factor, then the short-circuit withstand capability improves, but the manufacturing precision requirements increase
Solution Approach 1:
The patent specifies optimal ranges for doping concentration parameters (peak concentration between 1.0×10^16 to 1.0×10^18/cm³, integrated concentration between 1.0×10^12 to 1.0×10^14/cm²) that balance short-circuit withstand capability with manufacturing feasibility. These parameter ranges are designed to achieve the desired performance while accommodating normal manufacturing variations.
Data Source
AI summary
A semiconductor device is provided comprising: a semiconductor substrate; a drift region having a first conductivity type formed in the semiconductor substrate; a collector region having a second conductivity type, in the semiconductor substrate, formed between the lower surface of the semiconductor substrate and the drift region; and a high concentration region having a first conductivity type, in the semiconductor substrate, formed between the drift region and the collector region and having higher doping concentration than that in the drift region, wherein a doping concentration distribution of the high concentration region in the depth direction of the semiconductor substrate comprises one or more peaks, wherein a distance between a first peak closest to the lower surface side of the semiconductor substrate among the peaks of the doping concentration distribution of the high concentration region and the lower surface of the semiconductor substrate is 3 μm or less.