Semiconductor Device Impurity Concentration Optimization
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Solution Overview
Problem
Existing semiconductor devices with nonvolatile memory and capacitive elements on the same substrate face challenges in improving both memory and capacitive element performance simultaneously, leading to suboptimal device performance.
Innovation Solution
A semiconductor device design where the concentration of impurities in the upper electrode of the capacitive element is higher than in the memory gate electrode, with a manufacturing method involving specific layer formation and ion implantation to optimize the performance of both components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a single polysilicon layer is used for both memory gate electrode and capacitive element upper electrode, then manufacturing complexity is reduced, but performance optimization of both components becomes difficult
Solution Approach 1:
The patent makes the polysilicon layer multi-functional by using the same base layer for both the memory gate electrode and the capacitive element upper electrode. Through selective ion implantation and masking techniques, a single polysilicon layer is differentiated into regions with different electrical properties, allowing one layer to serve multiple functions with different performance requirements.
Solution Approach 2:
The patent changes the impurity concentration parameter selectively in different regions of the polysilicon layer. By controlling the impurity concentration in the upper electrode region to be higher than in the memory gate electrode region, the electrical characteristics are optimized for each component's specific function while maintaining structural simplicity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances the performance of both nonvolatile memory and capacitive elements, improving the overall semiconductor device functionality by optimizing the impurity concentration and layer structure.
Implementation Method 1
ion-implanting impurities into the upper electrode using the second mask layer as an ion implantation blocking mask
Data Source
AI summary
A memory cell of a nonvolatile memory and a capacitive element are formed over the same semiconductor substrate. The memory cell includes a control gate electrode formed over the semiconductor substrate via a first insulating film, a memory gate electrode formed adjacent to the control gate electrode over the semiconductor substrate via a second insulating film, and the second insulating film having therein a charge storing portion. The capacitive element includes a lower electrode formed of the same layer of a silicon film as the control gate electrode, a capacity insulating film formed of the same insulating film as the second insulating film, and an upper electrode formed of the same layer of a silicon film as the memory gate electrode. The concentration of impurities of the upper electrode is higher than that of the memory gate electrode.