Semiconductor Device Impurity Concentration Threshold Voltage
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Solution Overview
Problem
Current semiconductor devices, such as HEMTs, face challenges in improving characteristics like mobility and threshold voltage, particularly in achieving normally-OFF operation and high mobility, due to limitations in impurity concentration and crystallinity across different regions.
Innovation Solution
The semiconductor device incorporates a layered structure with specific impurity concentrations and orientations, using AlxGa1-xN as a second layer and silicon carbide or other Group IV semiconductors, along with an insulating portion, to create regions with varying impurity concentrations and crystallinity, allowing for the formation of two-dimensional electron or hole gases and adjusting threshold voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If impurity concentration is increased to obtain normally-OFF operation, then threshold voltage is improved, but mobility deteriorates
Solution Approach 1:
The patent applies local quality by creating distinct regions with different impurity concentrations within the semiconductor layer. Specifically, a first region with higher impurity concentration is formed adjacent to the gate electrode to establish normally-OFF operation and appropriate threshold voltage, while a second region with lower impurity concentration is formed in the channel area to maintain high electron mobility. This spatial differentiation of impurity concentrations allows simultaneous optimization of both threshold voltage and mobility characteristics.
Solution Approach 2:
The semiconductor layer is segmented into multiple functional regions with different impurity concentrations. The layer is divided into a first region (higher impurity concentration) near the gate electrode and a second region (lower impurity concentration) in the channel area. This segmentation enables independent optimization of electrical characteristics in different regions, allowing the device to achieve both normally-OFF operation and high mobility performance.
2Ease of manufacture
If uniform impurity concentration is used across the semiconductor layer, then manufacturing is simplified, but device characteristics cannot be optimized
Solution Approach 1:
Rather than using uniform impurity concentration, the patent implements local quality by establishing different impurity concentration levels in different regions of the semiconductor layer. The first region adjacent to the gate electrode has higher impurity concentration to ensure normally-OFF operation, while the second region in the channel has lower impurity concentration to maximize electron mobility. This approach prioritizes device performance optimization over manufacturing simplicity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables high mobility and normally-OFF operation by controlling carrier generation and concentration, resulting in improved semiconductor device characteristics.
Implementation Method 1
allowing for the formation of two-dimensional electron or hole gases and adjusting threshold voltage
Data Source
AI summary
According to one embodiment, a semiconductor device includes first to third electrodes, and first and second layers. A direction from the first electrode toward the second electrode is aligned with a first direction. A position in the first direction of the third electrode is between positions in the first direction of the first and second electrodes. The first layer includes at least one selected from the group consisting of silicon carbide, silicon, carbon, and germanium. The first layer includes first to sixth partial regions. A concentration of the first impurity in the fourth partial region is higher than a concentration of the first impurity in the fifth partial region and higher than a concentration of the first impurity in the sixth partial region. The second layer includes AlxGa1-xN (0<x≤1). The second layer includes a first portion and a second portion.