Semiconductor Device Integrating DRAM and Variable Resistance Memory
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Solution Overview
Problem
Next-generation semiconductor memory devices require improved integration of volatile and nonvolatile memory sections with different operating characteristics on a single substrate, while maintaining high performance and low power consumption.
Innovation Solution
A semiconductor device design featuring a first memory section with DRAM cell arrays and a second memory section with variable resistance memory cell arrays, both integrated on a substrate with distinct peripheral circuits and wiring patterns, allowing for efficient data storage and retrieval with different operating characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If volatile memory (DRAM) and nonvolatile memory (variable resistance memory) are integrated on a single substrate, then data storage capabilities and operational efficiency are enhanced, but device complexity and manufacturing difficulty increase due to different operating characteristics and structural requirements
Solution Approach 1:
The substrate is divided into a first memory section for volatile memory (DRAM) and a second memory section for nonvolatile memory (variable resistance memory), with each section having its own dedicated peripheral circuits. This segmentation allows each memory type to operate independently with its own optimized circuitry, reducing interference while maintaining integration benefits.
Solution Approach 2:
The patent utilizes vertical stacking to position the second memory section (nonvolatile) at a higher level than the first memory section (volatile) on the substrate. This three-dimensional arrangement allows both memory types to coexist without planar interference, enabling integration while maintaining distinct operational characteristics.
2Productivity
If distinct peripheral circuits are provided for each memory section, then operational efficiency is improved, but device complexity and area occupation increase
Solution Approach 1:
Each memory section is equipped with its own dedicated peripheral circuits tailored to its specific operational requirements. The first peripheral circuit section is optimized for DRAM operations while the second peripheral circuit section is optimized for variable resistance memory operations, allowing each section to operate at peak efficiency without compromising the other.
3Reliability
If wiring patterns are arranged at different levels to connect memory sections, then signal interference is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The wiring patterns are arranged in three-dimensional space with different levels, where the first wiring section connects to the first memory section and the second wiring section connects to the second memory section at a different vertical level. This spatial separation reduces signal interference between the two memory types while maintaining manageable manufacturing requirements through standardized multi-layer interconnect processes.
Data Source
AI summary
A semiconductor device including: a first memory section, a first peripheral circuit section, and a second peripheral circuit section on a substrate; a second memory section on the second peripheral circuit section; and a wiring section between the second peripheral circuit section and the second memory section, the first memory section includes a plurality of first memory cells, the first memory cells each including a cell transistor and a capacitor connected to the cell transistor, the second memory section includes a plurality of second memory cells, the second memory cells each including a variable resistance element and a select element in series, and the wiring section includes a plurality of line patterns, at least one of the line patterns and at least one of the capacitors at the same level from the substrate, the second memory cells are higher from the substrate than the at least one of the capacitors.