Semiconductor Device With Deeper I/O Diffusion Regions
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Solution Overview
Problem
The challenge is to enhance the breakdown voltage of semiconductor devices while maintaining miniaturization, as increasing the area of the I/O region to achieve higher breakdown voltage complicates device miniaturization and increases manufacturing costs.
Innovation Solution
The solution involves forming gate electrodes and source/drain regions with specific depth and structure differences between the I/O and logic regions, using a deeper n+-type semiconductor region in the I/O region to increase breakdown voltage without compromising device size, and employing an ONO film and silicon film stack to prevent impurity ion penetration during ion implantation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the area of the I/O region is increased to improve breakdown voltage, then the breakdown voltage of the semiconductor device is improved, but the device miniaturization becomes difficult
Solution Approach 1:
The patent applies local quality by creating different diffusion region depths in different regions of the semiconductor device. Specifically, the I/O region has a first diffusion region extending deeper from the surface than the second diffusion region in the logic region, allowing each region to be optimized for its specific function (higher breakdown voltage in I/O, standard performance in logic) without compromising overall device miniaturization
Solution Approach 2:
The patent transitions from two-dimensional area-based breakdown voltage improvement to three-dimensional depth-based improvement. By extending the first diffusion region deeper into the substrate compared to the second diffusion region, the invention achieves higher breakdown voltage in the I/O region without increasing the planar area, thus enabling device miniaturization while maintaining reliability
2Reliability
If the area of the I/O region is increased to improve breakdown voltage, then the breakdown voltage of the semiconductor device is improved, but manufacturing costs increase
Solution Approach 1:
The patent implements local quality through region-specific diffusion depths, where the first diffusion region in the I/O region extends deeper than the second diffusion region in the logic region. This localized structural differentiation achieves the required breakdown voltage improvement only where needed (in the I/O region), avoiding the need to increase the overall device area or implement complex manufacturing processes across the entire chip, thereby controlling manufacturing costs while improving reliability
3Reliability
If gate electrodes are formed at different levels with different diffusion region depths, then the breakdown voltage is improved, but the device structure becomes more complex
Solution Approach 1:
The patent applies local quality by implementing different diffusion region depths and gate electrode levels only in specific regions (I/O region versus logic region) rather than throughout the entire device. This localized approach achieves the necessary breakdown voltage improvement while limiting structural complexity to only the areas where it is functionally required, maintaining relative simplicity in the majority of the device structure
Solution Approach 2:
The patent segments the semiconductor device into distinct regions (I/O region and logic region) with different structural characteristics. The first diffusion region and second diffusion region are formed with different depths, and gate electrodes are positioned at different levels in different regions. This segmentation allows each region to be optimized independently, achieving high breakdown voltage where needed while maintaining overall device manageability and reducing the complexity burden across the entire structure
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively increases the breakdown voltage of the semiconductor device while maintaining miniaturization, improving reliability against noise-induced malfunctions and electromagnetic interference.
Implementation Method 1
employing an ONO film and silicon film stack to prevent impurity ion penetration during ion implantation
Data Source
AI summary
In a semiconductor device including a higher-breakdown-voltage MISFET, an improvement is achieved in the breakdown voltage of the MISFET, while preventing an increase in the area of the MISFET. A gate pattern including a gate electrode of the higher-breakdown-voltage MISFET is formed higher in level than a gate pattern including a gate electrode of a lower-breakdown-voltage MISFET. An n+-type semiconductor region included in each of source/drain regions of the higher-breakdown-voltage MISFET is formed deeper than an n+-type semiconductor region included in each of source/drain regions of the lower-breakdown-voltage MISFET.