Semiconductor Device Merging Pinned and Free Layers
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Solution Overview
Problem
The complexity and cost of manufacturing high-performance semiconductor memory devices, such as MRAM, are increased by the need for intricate multi-layered structures and precise etching processes, particularly in forming memory cells with magnetic tunnel junctions and selection elements.
Innovation Solution
A semiconductor device design featuring first and second line structures with pinned and free layers, respectively, and a tunnel barrier layer, simplifies the fabrication process by forming island-shaped stacked structures of tunnel barrier, free, and selection elements, reducing etching difficulties and specific resistivity, while maintaining data storage capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If intricate multi-layered structures and precise etching processes are used to form memory cells with magnetic tunnel junctions, then data storage performance is improved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent combines the pinned layer, free layer, and selection element into a single integrated line structure. This merging eliminates the need for separate formation processes for each component and reduces the number of etching steps required, thereby simplifying manufacturing while maintaining the functional performance of magnetic tunnel junctions for data storage
2Reliability
If intricate multi-layered structures and precise etching processes are used to form memory cells with magnetic tunnel junctions, then data storage performance is improved, but manufacturing cost increases
Solution Approach 1:
The patent combines the pinned layer, free layer, and selection element into a single integrated line structure. This merging eliminates the need for separate formation processes for each component and reduces the number of etching steps required, thereby simplifying manufacturing while maintaining the functional performance of magnetic tunnel junctions for data storage
3Reliability
If the thickness of the first line structure is increased to enhance stability, then operating characteristics improve, but device miniaturization becomes more difficult
Solution Approach 1:
The patent combines the pinned layer, free layer, and selection element into a single integrated line structure. This merging eliminates the need for separate formation processes for each component and reduces the number of etching steps required, thereby simplifying manufacturing while maintaining the functional performance of magnetic tunnel junctions for data storage
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design simplifies the manufacturing process, reduces manufacturing costs, and enhances the stability and operating characteristics of memory devices by increasing the thickness of the first line structure, thereby improving miniaturization and data storage reliability.
Implementation Method 1
a first tunnel barrier layer interposed between the first line structure and the first free layer
Implementation Method 2
a first pinned layer exhibiting a magnetization in a fixed magnetization direction
Implementation Method 3
a plurality of first free layers each exhibiting a magnetization with a magnetization direction that is changeable
Data Source
AI summary
A semiconductor device includes a plurality of first line structures extending in a first direction, each of the plurality of first line structures including a first pinned layer exhibiting a magnetization in a fixed magnetization direction; a plurality of second line structures spaced apart from the first line structures and extending in a second direction intersecting the first direction; a plurality of first free layers each exhibiting a magnetization with a magnetization direction that is changeable, the first free layers respectively overlapping intersection regions of the first line structures and the second line structures between the first line structures and the second line structures; and a first tunnel barrier layer interposed between the first line structure and the first free layer.