3D Nested Cavity Semiconductor Device Layout Area Reduction
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Solution Overview
Problem
The development of thin film transistors (TFTs) is limited by the need for increased output current, which requires larger dimensions, thereby reducing space for other circuit wires or components and affecting the aperture ratio of pixel electrodes in limited panel areas.
Innovation Solution
A semiconductor device with a substrate featuring a series of nested cavities and layers, including a metal layer, insulating layer, semiconductor layer, drain, and source, which occupies a smaller layout area, allowing for increased space for other components and enhancing the aperture ratio by using a three-dimensional structure with a semiconductor layer that covers inner walls of cavities and includes a three-dimensional connecting circuit with conductive layers and a filled material.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the dimension of the TFT is increased to increase output current, then the output current is improved, but the layout area increases and the aperture ratio is reduced
Solution Approach 1:
The patent transitions from a conventional planar TFT structure to a three-dimensional structure by forming cavities within the substrate and positioning the semiconductor layer, drain, and source within these cavities. This vertical integration allows the TFT to achieve longer channel lengths and larger dimensions without increasing the horizontal layout area, thereby maintaining high output current while preserving aperture ratio.
Solution Approach 2:
The patent implements nesting by placing the semiconductor layer, drain, and source inside cavities that are formed within the substrate. This nested configuration allows the TFT components to be embedded in the substrate volume rather than occupying additional planar space, effectively increasing the functional dimensions of the TFT without expanding the overall device footprint.
2Power
If the dimension of the TFT is increased to increase output current, then the output current is improved, but the aperture ratio is reduced
Solution Approach 1:
By moving the TFT structure into the third dimension through substrate cavities, the patent achieves longer channel lengths and improved current drive capability without expanding the pixel's horizontal footprint. This allows the pixel electrode to maintain a larger visible area (aperture ratio) while the TFT gains the dimensional space needed for higher output current.
3Area of stationary object
If the layout area is reduced to increase space for other components, then the aperture ratio is improved, but the TFT dimension is reduced and output current decreases
Solution Approach 1:
The patent embeds the TFT components (semiconductor layer, drain, source) within cavities formed in the substrate, creating a nested configuration that increases the effective dimensions of the TFT without increasing the horizontal layout area. This allows other pixel components to occupy more space while the TFT maintains sufficient channel length for high output current.
Data Source
AI summary
A semiconductor device including a substrate, a metal layer, an insulating layer, a semiconductor layer, a drain and a source is provided. The substrate has a surface and a first cavity. The metal layer is disposed on the substrate and covers the surface and inner-wall of the first cavity to define a second cavity corresponding to the first cavity. The insulating layer covers the metal layer and inner-wall of the second cavity to define a third cavity corresponding to the second cavity. The semiconductor layer exposes a portion of the insulating layer and covers the inner-wall of the third cavity to define a fourth cavity corresponding to the third cavity. The drain and source are disposed on the semiconductor layer and covers a portion of the semiconductor layer and a portion of the insulating layer, in which the drain and source expose the fourth cavity.