Semiconductor Device Structure Integrating Non-Volatile Memory and Logic
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Solution Overview
Problem
The increasing demand for higher integration density, lower power consumption, and mobility in semiconductor devices, particularly driven by IoT and mobile applications, poses challenges in developing non-volatile memory devices that can be seamlessly integrated with logic devices using advanced fabrication techniques without increasing the complexity or power consumption.
Innovation Solution
A semiconductor device structure is formed by integrating a non-volatile memory device with a logic device on a shared semiconductor substrate, where the non-volatile memory device comprises a floating-gate, select gates, and control gates separated by insulating material layers, and the logic device is fabricated in a separate region, allowing for efficient integration and reduced power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If non-volatile memory devices are integrated with logic devices on the same semiconductor substrate, then integration density is improved, but device complexity increases
Solution Approach 1:
The patent divides the semiconductor substrate into distinct first and second regions, with the non-volatile memory device structure formed in the first region and the logic device formed in the second region. This spatial segmentation allows both device types to coexist on the same substrate while maintaining separate optimization for each function, thereby increasing integration density without excessively complicating the overall device architecture.
Solution Approach 2:
The patent creates a unified semiconductor substrate that serves multiple functions by integrating both non-volatile memory and logic devices. The shared substrate provides a common foundation that supports diverse device structures, enabling the system to achieve high integration density while managing complexity through a standardized platform approach.
2Reliability
If non-volatile memory device structure is formed with multiple gates and insulating layers, then memory functionality is improved, but manufacturing complexity increases
Solution Approach 1:
The non-volatile memory device structure is segmented into distinct functional components including a floating gate, select gates, control gates, and insulating material layers. Each component is formed in a specific sequence and position, allowing the complex memory functionality to be achieved through modular construction that can be integrated into standard fabrication flows.
Solution Approach 2:
The floating gate is formed before the control gate in the fabrication sequence. This preliminary action of creating the floating gate structure first establishes the foundation for subsequent gate formations and insulating layer deposits, enabling the complex multi-gate architecture to be built systematically while maintaining compatibility with existing manufacturing processes.
3Ease of manufacture
If floating gate is formed before control gate, then manufacturing simplicity is improved, but process sequence complexity increases
Solution Approach 1:
The floating gate is formed as a preliminary structure before the control gate is created. This sequencing simplifies the overall manufacturing process by establishing the floating gate foundation early, which then guides subsequent fabrication steps for the control gate and insulating layers, making the complex multi-gate structure more manufacturable.
Solution Approach 2:
The gate formation process is segmented into distinct stages: floating gate formation, followed by control gate formation. This temporal segmentation of the manufacturing process allows each gate structure to be optimized independently while maintaining a clear, manageable fabrication sequence that reduces overall process complexity.
Data Source
AI summary
The present disclosure provides a semiconductor device structure including a non-volatile memory (NVM) device structure in and above a first region of a semiconductor substrate and a logic device formed in and above a second region of the semiconductor substrate different from the first region. The NVM device structure includes a floating-gate, a first select gate and at least one control gate. The logic device includes a logic gate disposed on the second region and source/drain regions provided in the second region adjacent to the logic gate. The control gate extends over the floating-gate and the first select gate is laterally separated from the floating-gate by an insulating material layer portion. Upon forming the semiconductor device structure, the floating gate is formed before forming the control gate and the logic device.