Semiconductor Device Reducing Parasitic Capacitance
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Solution Overview
Problem
High-side power ICs experience error operations due to parasitic capacitance caused by polysilicon-insulator-polysilicon (PIP) capacitive elements, which increases with thinner insulating films and larger polysilicon layers, leading to capacitive coupling between high-potential terminals and internal circuits.
Innovation Solution
A semiconductor device structure is implemented with a semiconductor base body of a first conductivity-type, including a first electrode, a first semiconductor region of a second conductivity-type, a second semiconductor region of the first conductivity-type, an insulating film, and a passive element on the insulating film, where the first and second semiconductor regions are arranged to promote depletion and reduce parasitic capacitance by connecting the passive element.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the insulating film thickness is reduced to improve process shrink, then manufacturing precision is improved, but parasitic capacitance increases
Solution Approach 1:
The invention extracts and removes the harmful polysilicon film at the lower layer of the PIP capacitive element. By eliminating this conductive layer, the parasitic capacitance between the high-potential terminal and internal circuits is significantly reduced, while maintaining the desired thin insulating film structure for process shrink improvement.
Solution Approach 2:
The invention converts the harmful effect of polysilicon layers into a beneficial structure by replacing them with an insulating film. This transformation eliminates the parasitic capacitance problem while preserving the capacitive function of the PIP element, turning a potential source of error operations into a reliable circuit component.
2Reliability
If polysilicon layers are made larger to improve capacitance function, then the capacitive element performance is improved, but parasitic capacitance increases
Solution Approach 1:
The invention extracts and removes the lower polysilicon layer that causes parasitic capacitance, while preserving the upper polysilicon layer and insulating layer that provide the desired capacitance function. This selective removal maintains capacitive performance while eliminating the harmful parasitic effect.
Solution Approach 2:
The invention applies different material properties to different parts of the capacitive element structure. The upper layer uses conductive polysilicon for capacitance, while the lower layer uses insulating material to prevent parasitic capacitance, creating local quality differentiation that resolves the contradiction.
3Adaptability or versatility
If a PIP capacitive element is provided on a high-side power IC, then the device functionality is improved, but error operation occurs due to parasitic capacitance
Solution Approach 1:
The invention converts the harmful parasitic capacitance effect into a beneficial low-parasitic structure by replacing the lower polysilicon layer with an insulating film. This allows the PIP capacitive element to function reliably in high-side power IC applications without causing error operations, improving both adaptability and reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The structure effectively reduces parasitic capacitance connected to the passive element, suppressing error operations in the circuit by depleting the regions under the passive element and series-combining depletion layer capacitances with oxide film capacitances to minimize overall parasitic capacitance.
Implementation Method 1
the first and second semiconductor regions are arranged to promote depletion and reduce parasitic capacitance by connecting the passive element
Data Source
AI summary
A semiconductor device includes: a semiconductor base body of a first conductivity-type; a first electrode electrically connected to the semiconductor base body; a first semiconductor region of a second conductivity-type provided at an upper part of the semiconductor base body; a second semiconductor region of the first conductivity-type provided at an upper part of the first semiconductor region; a second electrode electrically connected to the first semiconductor region; an insulating film provided on a top surface of the second semiconductor region; and a passive element provided on a top surface of the insulating film.