Semiconductor Device Parasitic Capacitance Reduction
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Solution Overview
Problem
Existing semiconductor devices, particularly high electron mobility transistors (HEMTs), face challenges in reducing device output capacitance and parasitic capacitances, which affect their performance and efficiency in power control applications.
Innovation Solution
The semiconductor device design includes a compound semiconductor material with a dielectric material in the non-device region and electrodes, where the dielectric material surrounds the electrically conductive material and pads are arranged on it, reducing the influence of the conductive substrate and minimizing parasitic capacitances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If pads are directly arranged on the conductive substrate, then electrical connection is achieved, but parasitic capacitances increase significantly
Solution Approach 1:
A dielectric material is introduced as an intermediary layer between the conductive substrate and the pads. This dielectric layer acts as a mediator that electrically isolates the pads from the substrate, thereby reducing parasitic capacitances while maintaining proper electrical connections through designated contact regions.
Solution Approach 2:
The dielectric material is segmented to create specific contact regions where electrical connection is permitted. By dividing the dielectric layer into regions with different properties (contact regions versus insulating regions), the patent achieves both electrical connection where needed and capacitance reduction where not needed.
2Object-generated harmful factors
If device region is surrounded by non-device region with dielectric material, then parasitic capacitances are reduced, but device complexity increases
Solution Approach 1:
The dielectric material is applied selectively only in the non-device region surrounding the active device area, rather than uniformly across the entire substrate. This local application reduces parasitic capacitances in critical areas while avoiding unnecessary complexity in the active device region.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design significantly decreases parasitic gate-to-source and drain-to-source capacitances, typically by three times, improving the device's performance and reducing device output capacitance, enhancing power control efficiency.
Implementation Method 1
reduces parasitic gate-to-source and drain-to-source capacitances
Implementation Method 2
providing a dielectric material in the non-device region
Data Source
AI summary
A semiconductor device includes a device region including a compound semiconductor material and a non-device region at least partially surrounding the device region. The semiconductor device further includes a dielectric material in the non-device region and at least one electrode in the device region. The semiconductor device further includes at least one pad electrically coupled to the at least one electrode, wherein the at least one pad is arranged on the dielectric material in the non-device region.