Semiconductor Device Patterning for Peripheral Circuit Fineness
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Solution Overview
Problem
Peripheral circuits in semiconductor devices, such as DRAM, face challenges in achieving fine patterns due to non-uniform line widths and two-dimensional configurations, making it difficult to improve fineness and fill gaps in pattern pitch using high-NA exposure conditions.
Innovation Solution
The semiconductor device employs a specific layout and fabrication method involving multiple wiring layers and insulating films, with distinct patterning processes for pads and wiring layers to achieve a line and space layout with minimum dimensions and pitch, ensuring electrical continuity while avoiding shorts and allowing for reduced chip area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If high-NA exposure conditions with high resolution are used, then memory cell pattern fineness is improved, but peripheral circuit patterning becomes difficult due to non-uniform line widths and two-dimensional patterns
Solution Approach 1:
The patent divides the chip into two distinct regions: a memory cell region with high-density repetitive patterns and a peripheral circuit region with non-uniform two-dimensional patterns. Each region can be optimized independently, allowing high-NA exposure to be applied selectively to the memory cell region where it provides benefit, while the peripheral circuit region uses conventional exposure methods suited to its pattern characteristics.
Solution Approach 2:
The patent applies different exposure conditions to different regions of the chip. The memory cell region receives high-NA exposure with strong interference effects optimized for fine repetitive patterns, while the peripheral circuit region uses conventional exposure conditions appropriate for non-uniform line widths and two-dimensional structures. This localized optimization resolves the contradiction between achieving fine patterns and accommodating diverse pattern types.
2Ease of manufacture
If conventional exposure conditions are used for peripheral circuits, then pattern formation is achievable, but pattern pitch gaps cannot be filled and fineness improvement is limited
Solution Approach 1:
The patent introduces a third dimension by forming insulating film stacks with varying heights (first insulating film with first thickness, second insulating film with second thickness greater than the first). This vertical dimensionality allows for differentiated processing and enables the peripheral circuit region to achieve better pattern fineness and pitch utilization through selective etching and planarization processes, effectively filling the gap left by conventional exposure limitations.
3Device complexity
If uniform patterning is applied across the entire chip, then process simplicity is maintained, but peripheral circuit performance suffers due to non-uniform line width requirements
Solution Approach 1:
The patent segments the patterning process into region-specific operations. The memory cell region undergoes high-NA exposure with optimized conditions for repetitive patterns, while the peripheral circuit region receives conventional exposure followed by selective processing steps including targeted etching of insulating films. This segmentation increases process complexity but is necessary to achieve the non-uniform line widths required for peripheral circuit performance and reliability.
Solution Approach 2:
The patent implements local quality by applying different processing conditions to different chip regions. The peripheral circuit region receives customized processing including selective removal of the second insulating film in specific areas, allowing optimization of line widths and spacing for amplifier and driver circuits. This localized optimization is essential for achieving the non-uniform patterns required for reliable peripheral circuit operation.
Data Source
AI summary
A semiconductor device includes a first layer including a plurality of wirings arranged in line and space layout and a second layer including a pad electrically connected to at least one of the wirings, wherein the wirings and the pads are patterned by different lithographic processes.