Semiconductor Device With Dual-Permittivity Sealing Member

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Solution Overview

Problem

Semiconductor devices face a decrease in electrostatic breakdown voltage due to rapid electrostatic discharge as a result of miniaturization, leading to concerns about charged-device model (CDM) breakdown, especially with increasing package capacity.

Innovation Solution

A semiconductor device design incorporating a substrate, semiconductor chip, and a sealing member with a first sealing member made of non-porous material and a second sealing member made of porous material, where the permittivity of the second sealing member is lower than the first, effectively reducing parasitic capacitance and preventing electrostatic breakdown.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Strength

If the package capacity is increased, then the mechanical strength is improved, but the electrostatic breakdown voltage decreases

Engineering Contradiction:

Improvemechanical strengthVSAvoidelectrostatic breakdown voltage

Core Design Contradiction:

StrengthVSReliability

Solution Approach 1:

The sealing member is divided into two regions with different permittivities: a first region with higher permittivity and a second region with lower permittivity. This local differentiation allows the package to have sufficient mechanical strength while reducing parasitic capacitance in critical areas, thereby preventing electrostatic breakdown.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The sealing member is constructed as a composite structure with two different materials having different permittivity values. The first sealing member material provides mechanical strength, while the second sealing member material with lower permittivity reduces parasitic capacitance, achieving both mechanical reliability and electrostatic protection.

Inventive Principle:

Principle #40Composite materials

2Stability of the object's composition

If the package capacity is increased, then the structural stability is improved, but the parasitic capacitance increases

Engineering Contradiction:

Improvestructural stabilityVSAvoidparasitic capacitance

Core Design Contradiction:

Stability of the object's compositionVSQuantity of substance

Solution Approach 1:

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The second sealing member material may be a porous material with lower permittivity compared to the first sealing member material. The porous structure reduces the dielectric constant, thereby reducing parasitic capacitance while maintaining adequate mechanical properties.

Inventive Principle:

Principle #31Porous materials

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The design enhances mechanical strength, moisture resistance, and insulation resistance while reducing electrostatic breakdown and package capacity, effectively addressing the challenge of decreasing electrostatic breakdown voltage.

Implementation Method 1

A permittivity of the second sealing member is lower than a permittivity of the first sealing member

Methodology Applied

Scientific EffectPermittivity: Dielectric Permittivity

Implementation Method 2

a first sealing member and a second sealing member, the second sealing member facing at least a part of the second principal surface, and a permittivity of the second sealing member being lower than a permittivity of the first sealing member

Methodology Applied

Scientific EffectPorosity: Porosity

Data Source

PatentUS11342287B2Semiconductor device

Publication Date: 2022.05.24 KIOXIA CORP

AI summary

A semiconductor device includes a substrate, a semiconductor chip, and a sealing member. The semiconductor chip is disposed on the substrate. The semiconductor chip includes a first principal surface on a side of the substrate and a second principal surface on a side opposite to the first principal surface. The sealing member seals the semiconductor chip. The sealing member includes a first sealing member and a second sealing member. The second sealing member faces at least a part of the second principal surface. A permittivity of the second sealing member is lower than a permittivity of the first sealing member.