Semiconductor Device Separate Source Lead Traces Parasitic Inductance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
High parasitic inductance in the internal lead traces of power semiconductor chips leads to delayed turn-on switching and increased power loss in DC-DC converters, especially at higher frequencies and currents, which deteriorates power conversion efficiency.
Innovation Solution
The semiconductor device incorporates separate source lead traces and a distinct ground path for the drive circuit, reducing the influence of parasitic inductance and allowing for faster switching without delaying turn-on and turn-off, thereby improving power conversion efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If separate source lead traces and distinct ground path are used, then power conversion efficiency is improved, but device complexity increases
Solution Approach 1:
The source lead traces are divided into first and second separate traces, with the first source lead trace connected to the first source terminal and the second source lead trace connected to the second source terminal. This segmentation allows the main current path and gate drive return path to be physically separated, reducing parasitic inductance effects and improving power conversion efficiency.
Solution Approach 2:
The gate drive return path is extracted and separated from the main current path by using a distinct second source lead trace. This extraction eliminates the coupling between high-current switching transients and the gate drive circuit, preventing turn-on delay caused by parasitic inductance voltage drops.
2Productivity
If higher frequency and current are used, then productivity is improved, but parasitic inductance effects worsen
Solution Approach 1:
By segmenting the source connections into separate lead traces, the patent enables high-frequency operation with reduced parasitic inductance effects. The separation ensures that high-frequency switching currents do not induce voltage drops in the gate drive path, maintaining switching performance at higher frequencies.
Solution Approach 2:
The patent adds a dimensional aspect to the trace layout by using multiple separate traces instead of a single shared path. This spatial separation in the trace dimension reduces the loop area and parasitic inductance, enabling higher switching frequencies without the harmful effects of parasitic inductance.
3Power
If main current flows through parasitic inductance, then power loss increases, but switching speed must be maintained
Solution Approach 1:
The gate drive return path is extracted from the main current path by using a separate second source lead trace. This prevents the main current from flowing through the gate drive loop, eliminating the induced electromotive force that would otherwise slow down turn-on switching while maintaining high switching speed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration significantly reduces power loss and enhances the efficiency of power conversion in high-frequency and high-current applications by minimizing the impact of parasitic inductance on the gate-source voltage, leading to improved performance in power supply circuits like DC-DC converters.
Implementation Method 1
parasitic inductance occurs due to wire bonding or printed circuit board traces of the package. In particular, when a main current flows through the parasitic inductance at the source terminal of the high-side switch, great induced electromotive force is generated.
Implementation Method 2
when a main current flows through the parasitic inductance at the source terminal of the high-side switch, great induced electromotive force is generated
Data Source
AI summary
A switching device includes a power semiconductor chip, and a drive circuit which drives the power semiconductor chip. In the power semiconductor chip, a path through which a main current flows is connected to a first source terminal, and a ground terminal of the drive circuit is connected to a second source terminal of the power semiconductor chip. As a result, a gate drive path is separated from the path through which the main current flows, and therefore, the influence of induced electromotive force which is generated due to source parasitic inductance, on a gate-source voltage, is reduced.