Semiconductor Device Single-Layer Polysilicon Gate Layout
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Solution Overview
Problem
Nonvolatile memory devices with double-layer polysilicon gates face complex manufacturing processes and higher costs due to the difficulty in achieving reliable electrical isolation between polysilicon layers, whereas single-layer polysilicon gate devices require more chip area for equivalent functionality.
Innovation Solution
A semiconductor device design where nonvolatile memory cells with single-layer polysilicon gates are arranged to share active regions for write/erase and read elements, reducing chip area by optimizing the layout and structure of memory cells on a semiconductor substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a double-layer polysilicon gate structure is used in nonvolatile memory, then data storage reliability is improved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent merges the control gate and floating gate into a single polysilicon layer structure, where the same polysilicon layer serves both as the control gate electrode and contains the floating gate region. This integration eliminates the need for separate polysilicon layers and complex isolation processes between them, thereby reducing manufacturing complexity while maintaining the essential charge storage functionality for reliability
Solution Approach 2:
The single polysilicon gate layer performs multiple functions: it acts as the control gate for channel modulation, contains the floating gate region for charge storage, and eliminates the need for separate isolation structures between gates. This multi-functionality reduces the overall device complexity and manufacturing steps while preserving the dual functionality needed for reliable operation
2Device complexity
If a single-layer polysilicon gate structure is used in nonvolatile memory, then manufacturing complexity is reduced, but chip area increases
Solution Approach 1:
The patent utilizes vertical stacking of functional regions within the single polysilicon gate layer, arranging the control gate, floating gate, and channel regions in a vertically integrated configuration. This three-dimensional arrangement allows multiple functional elements to occupy overlapping horizontal spaces, thereby reducing the overall chip area while maintaining the simplified single-layer structure
Solution Approach 2:
The floating gate region is nested within the same polysilicon layer that forms the control gate, with the channel region positioned beneath both. This nested configuration allows the functional elements to share horizontal space efficiently, reducing the total chip area required while maintaining the single-layer simplified manufacturing approach
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design reduces the chip area required for nonvolatile memory devices while maintaining reliable data storage and retrieval operations, simplifying the manufacturing process and lowering costs.
Implementation Method 1
allowing a FN (Fowlor Nordheim) tunnel current to flow via the tunnel portion and causing the injection of electrons into the floating gate or the emission of electrons from the floating gate
Data Source
AI summary
The chip area of a semiconductor device including a nonvolatile memory is reduced. The semiconductor device includes a first memory cell and a second memory cell which are formed on the principal surface of a substrate, and arranged adjacent to each other. In a principal surface of the substrate, active regions which are electrically isolated from each other are arranged. In the first active region, the capacitor element of the first memory cell is arranged, while the capacitor element of the second memory cell is arranged in the fourth active region. In the second active region, the respective write/erase elements of the first and second memory cells are both arranged. Further, in the third active region, the respective read elements of the first and second memory cells are both arranged.