Semiconductor Device With Vertically Stacked Gate Lines
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Solution Overview
Problem
The integration degree of 2-dimensional memory semiconductor devices is limited by the cost and complexity of forming fine patterns, which restricts the increase in the level of integration.
Innovation Solution
A semiconductor device with vertically stacked gate lines and semiconductor patterns that connect upper and lower interconnections, featuring a zigzag-shaped cross-section with horizontal and vertical portions, allowing for increased integration density and efficient data storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If fine pattern formation technology is used to increase integration degree, then the integration degree increases, but the manufacturing cost increases
Solution Approach 1:
The patent transitions from 2-dimensional planar memory structure to 3-dimensional vertical structure by stacking gate lines vertically. Multiple gate lines (first gate line, second gate line, third gate line) are positioned at different heights above the substrate, creating a vertical array that increases storage capacity without requiring finer lateral patterning. This dimensional change allows integration degree improvement while avoiding the cost penalties of advanced 2D lithography.
2Quantity of substance
If fine pattern formation technology is used to increase integration degree, then the integration degree increases, but the process complexity increases
Solution Approach 1:
The memory structure is segmented into multiple vertically stacked gate lines, each serving as an independent storage element. The first gate line, second gate line, and third gate line are formed as separate entities with distinct contact regions, allowing independent addressing and control. This segmentation enables higher integration through vertical stacking rather than through increasingly complex 2D patterning processes.
3Quantity of substance
If wiring portion length is reduced, then integration density increases, but manufacturing precision requirements increase
Solution Approach 1:
The patent reduces wiring portion length by transitioning from horizontal interconnection to vertical interconnection. The contact portions extend vertically from the substrate surface to connect with upper interconnections, eliminating the need for long horizontal wiring portions that would require precise lateral alignment. This vertical arrangement achieves high integration density while reducing the precision demands on lateral patterning.
Data Source
AI summary
Provided is a semiconductor device that can include a lower interconnection on a substrate and at least one upper interconnection disposed on the lower interconnection. At least one gate structure can be disposed between the upper interconnection and the lower interconnection, where the gate structure can include a plurality of gate lines that are vertically stacked so that each of the gate lines has a wiring portion that is substantially parallel to an upper surface of the substrate and a contact portion that extends from the wiring portion along a direction penetrating an upper surface of the substrate. At least one semiconductor pattern can connect the upper and lower interconnections.