Semiconductor Device With High Resistivity Layer for Switching Loss Control
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Solution Overview
Problem
Semiconductor devices with thin wafers face increased energy loss due to depletion layer reaching the rear surface, leading to reduced withstand voltage and higher leakage current, and existing solutions suffer from switching losses attributed to hole lifetime.
Innovation Solution
A semiconductor device is designed with a drift layer, a buffer layer of lower resistivity formed by impurity diffusion, and a high resistivity layer between the buffer layer and the rear surface, controlling hole lifetime and suppressing switching loss through specific implantation and heat treatment processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the semiconductor wafer is made thin to reduce energy loss, then the electric resistance is reduced, but the depletion layer reaches the rear surface resulting in decreased withstand voltage and increased leakage current
Solution Approach 1:
The patent applies local quality by creating a buffer layer with non-uniform impurity concentration distribution at the rear surface of the semiconductor wafer. The impurity concentration is highest at the surface and gradually decreases toward the drift layer, forming a gradient structure. This localized modification of electrical properties at the rear surface allows the depletion layer to be gently stopped, preventing it from reaching through to the front surface, thereby maintaining high withstand voltage while keeping the wafer thin for low energy loss.
2Reliability
If a buffer layer with higher impurity concentration is formed on the rear surface to stop the depletion layer, then the withstand voltage is improved, but switching loss occurs due to hole lifetime extension
Solution Approach 1:
The patent applies parameter changes by precisely controlling the impurity concentration gradient in the buffer layer. By optimizing the impurity concentration profile (highest at surface, decreasing toward drift layer) and adjusting the total impurity amount, the patent achieves a balance where the depletion layer is stopped effectively while hole lifetime is not excessively extended. This parameter optimization reduces switching loss compared to conventional uniform buffer layers, while maintaining adequate withstand voltage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively controls hole lifetime and reduces switching loss by forming a high resistivity layer that captures holes, enhancing the semiconductor device's energy efficiency and switching speed.
Implementation Method 1
a heat treatment step of forming a first buffer layer having a resistivity lower than that of the drift layer by diffusing the first conductivity type impurities
Implementation Method 2
a first implantation step of performing implantation of first conductivity type impurities into the semiconductor substrate in a depth direction from the second main surface toward the first main surface
Data Source
AI summary
Provided are a semiconductor device in which the lifetime of holes is controlled and the switching loss is suppressed, and a method of manufacturing the same. Provided are a semiconductor substrate having a drift layer of a first conductivity type between a first main surface and a second main surface opposite to the first main surface, a first buffer layer of the first conductive type provided between the drift layer and the second main surface in contact with the drift layer, having a resistivity lower than that of the drift layer, and having an impurity concentration higher than that of the drift layer, and a high resistivity layer provided between the first buffer layer and the second main surface and having a resistivity higher than that of the drift layer.