3D Stacked Semiconductor Device Via Through-Vias
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Solution Overview
Problem
The integration of CMOS image sensor and logic chips into a single chip for miniaturization in imaging devices faces challenges such as increased steps, high costs, and difficulty in maintaining both analog and logic characteristics, leading to noise issues and parasitic resistance and capacitance increases, which require special circuits for communication.
Innovation Solution
A semiconductor device with a support substrate connecting CMOS image sensor and image processing chips via through-vias and interconnects, eliminating the need for special communication circuits and reducing noise influence, while enhancing arrangement density and suppressing parasitic resistance and capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If two chips are connected using conventional methods, then the mounting area is reduced, but the arrangement pitch becomes small and yield is lowered
Solution Approach 1:
The patent transitions from planar chip connection to three-dimensional stacking connection. Chips are connected in the vertical direction (stacking) rather than side-by-side in the plane, allowing smaller mounting area while maintaining adequate arrangement pitch and yield through the vertical dimension.
Solution Approach 2:
Multiple chips are stacked and connected vertically like nested dolls, with each chip positioned above or below another. This nesting arrangement in the vertical direction reduces the overall footprint while maintaining proper spacing and connection quality between individual chips.
2Use of energy by moving object
If DC components are supplied from logic chip to CIS chip through conventional connections, then power supply is achieved, but noise influence from 1/f noise increases and special circuits are required
Solution Approach 1:
A dedicated power supply chip is introduced as an intermediary component between the logic chip and CIS chip. This mediator chip handles the DC power supply and reference signal distribution, isolating the noise-prone logic chip from the sensitive CIS chip and eliminating the need for special noise-filtering circuits.
Solution Approach 2:
The system is segmented into functionally independent chips: a logic chip for digital processing, a CIS chip for image sensing, and a separate power supply chip for DC distribution. This segmentation allows each chip to be optimized for its specific function while reducing cross-interference and noise coupling between different functional blocks.
3Area of stationary object
If chips are connected with small arrangement pitch, then mounting area is reduced, but parasitic resistance and capacitance increase
Solution Approach 1:
Connection paths are extended into the vertical dimension through stacking, allowing longer but more controlled interconnect paths. This enables reduced mounting area while managing parasitic effects through vertical routing rather than cramped horizontal routing.
Solution Approach 2:
The power supply chip acts as an intermediary with dedicated power and signal distribution structures. This mediator provides optimized connection paths with controlled impedance and reduced parasitic effects, even when chips are closely spaced in the stacking arrangement.
Data Source
AI summary
Disclosed herein is a solid state imaging device including a support substrate; an imaging semiconductor chip having a pixel array disposed on the support substrate; and an image processing semiconductor chip disposed on the support substrate, wherein the imaging semiconductor chip and the image processing semiconductor chip are connected by through-vias, and interconnects formed on the support substrate.