Semiconductor Device Single Dual Gate Transistor Parasitic Capacitance
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Solution Overview
Problem
Current semiconductor devices face challenges in achieving reduced parasitic capacitance and high on-state current while maintaining stable electrical characteristics, which are essential for advanced applications such as high-performance display devices.
Innovation Solution
A semiconductor device design featuring a first transistor with a single-gate structure and a second transistor with a dual-gate structure, both fabricated on the same insulating surface, utilizing a metal oxide semiconductor layer with specific insulating and conductive layer configurations to optimize electrical properties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a single transistor structure is used, then device complexity is reduced, but electrical characteristics cannot be optimized for different functions
Solution Approach 1:
The patent divides the transistor structure into two distinct types: a first transistor with a single gate electrode for reduced parasitic capacitance, and a second transistor with dual gate electrodes for high on-state current. This segmentation allows each transistor type to be optimized for specific electrical characteristics while maintaining overall device functionality.
Solution Approach 2:
Different gate structures are applied to different transistor locations based on functional requirements. The first transistor uses a single gate structure in regions where low parasitic capacitance is critical, while the second transistor uses dual gates in regions requiring high current drive capability, achieving local optimization of electrical properties.
2Speed
If parasitic capacitance is reduced, then signal transmission speed is improved, but on-state current capability is compromised
Solution Approach 1:
The patent segments the transistor population into two functional groups: first transistors with single gates optimized for high-speed signal transmission with low parasitic capacitance, and second transistors with dual gates optimized for high on-state current applications. This allows simultaneous optimization of both speed and current capability in different circuit locations.
Solution Approach 2:
Different gate configurations are deployed locally based on circuit requirements. Single-gate transistors are placed in signal path regions where speed is critical, while dual-gate transistors are placed in regions requiring high current drive, achieving local optimization of electrical performance.
3Reliability
If metal oxide semiconductor layer is used, then field-effect mobility is increased, but manufacturing precision requirements are heightened
Solution Approach 1:
The patent employs sputtering method parameters optimization to form metal oxide semiconductor layers with controlled thickness and composition. By adjusting sputtering power, gas flow ratios, and deposition temperature, the manufacturing process achieves the required layer precision while maintaining high field-effect mobility of the metal oxide material.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design achieves reduced parasitic capacitance and high on-state current, enabling stable electrical characteristics and reliable operation, suitable for high-performance display devices with improved signal transmission and reduced signal delay.
Implementation Method 1
a first insulating layer, a first semiconductor layer over the first insulating layer, a second insulating layer over the first semiconductor layer
Implementation Method 2
a first conductive layer overlapping with the first semiconductor layer with the second insulating layer interposed therebetween
Data Source
AI summary
A semiconductor device having favorable and stable electrical characteristics is provided. The semiconductor device includes a first and a second transistor over an insulating surface. The first and the second transistors each include a first insulating layer, a semiconductor layer over the first insulating layer, a second insulating layer over the semiconductor layer, and a first conductive layer overlapping with the semiconductor layer with the second insulating layer interposed therebetween. The first insulating layer includes a convex first region that overlaps with the semiconductor layer and a second region that does not and is thinner than the first region. The first conductive layer includes a part over the second region where a lower surface of the first conductive layer is positioned below a lower surface of the semiconductor layer. The second transistor further includes a third conductive layer overlapping with the semiconductor layer with the first insulating layer interposed therebetween.