Semiconductor Device Vertical Gate Stacking Buffer Layer
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The increasing demand for high-performance, high-speed, and multifunctional semiconductor devices has led to challenges in integrating semiconductor devices effectively, particularly in arranging gates in a vertical direction to enhance integration and reliability.
Innovation Solution
The semiconductor device incorporates a substrate with a lower structure featuring wiring structures and insulating layers, a pattern layer with a plate and via portion, and a graphene-like carbon material layer interposed between the via portion and the wiring structure, with gate layers stacked vertically and a memory vertical structure penetrating these layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If gates are arranged in a vertical direction to increase integration, then device integration is improved, but manufacturing complexity increases
Solution Approach 1:
The patent transitions from two-dimensional planar gate arrangement to three-dimensional vertical gate stacking. Multiple gate layers are arranged vertically above the substrate, enabling higher device integration by utilizing the vertical dimension for additional memory cells and structures.
Solution Approach 2:
The device is divided into multiple discrete gate layers stacked vertically, with each layer serving specific functions. The pattern layers are segmented into plate portions and via portions, allowing independent formation and optimization of different structural elements.
2Ease of manufacture
If a pattern layer is formed directly on wiring structures, then manufacturing steps are reduced, but contamination and defects occur in the polysilicon pattern layer
Solution Approach 1:
A buffer conductive layer is introduced as an intermediary between the wiring structures and the polysilicon pattern layer. This buffer layer prevents direct contact that causes contamination, while still enabling electrical connection through the via portions, thus improving pattern layer quality without significantly increasing manufacturing complexity.
3Reliability
If the via portion directly contacts the wiring structure, then electrical connection is achieved, but contamination occurs in the polysilicon pattern layer
Solution Approach 1:
The buffer conductive layer serves as a mediator between the via portion and the wiring structure. It maintains electrical connectivity while preventing metal contamination from the wiring structure from reaching and degrading the polysilicon pattern layer, thus preserving both electrical connection and pattern layer purity.
Solution Approach 2:
The buffer conductive layer is selectively positioned only where needed - at the interface between the via portion and wiring structure - providing localized protection against contamination while maintaining electrical connection, without affecting the overall pattern layer quality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves the reliability and integration of semiconductor devices by preventing contamination and defects in the polysilicon pattern layer, enhancing the overall performance and functionality of the device.
Implementation Method 1
a buffer conductive layer interposed between the via portion of the first pattern layer and the ground wiring structure so as to be in contact with the via portion and the ground wiring structure
Data Source
AI summary
A semiconductor device includes a substrate, a lower structure on the substrate, the lower structure including a first wiring structure, a second wiring structure, and a lower insulating structure covering the first and second wiring structures, a first pattern layer including a plate portion and a via portion, the plate portion being on the lower insulating structure and the via portion extending into the lower insulating structure from a lower portion of the plate portion and overlapping the first wiring structure, a graphene-like carbon material layer in contact with the via portion and the first wiring structure between the via portion and the first wiring structure, gate layers stacked in a vertical direction perpendicular to an upper surface of the substrate and spaced apart from each other on the first pattern layer, and a memory vertical structure penetrating through the gate layers in the vertical direction.