3D Gate-All-Around Semiconductor Device With Vertical Stacked Gates
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Solution Overview
Problem
Current semiconductor devices face challenges in increasing data storage capacity and reliability, particularly in achieving high integration and efficient data storage in electronic systems.
Innovation Solution
A semiconductor device design featuring a stack structure with vertically stacked gate electrodes, selection structures, and vertical structures that penetrate both the stack and selection structures, along with an upper isolation structure and horizontal dielectric patterns surrounding the selection gate electrodes, enhancing data storage capacity and integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If vertically stacked gate electrodes are used to increase data storage capacity, then storage density improves, but device complexity increases
Solution Approach 1:
The patent transitions from two-dimensional planar memory cells to three-dimensional vertically stacked gate electrodes, enabling multiple storage layers to be stacked along the vertical direction. This dimensional change allows significant increase in storage capacity without expanding the footprint area, directly resolving the contradiction between storage density and device complexity.
Solution Approach 2:
The patent implements nested structures where selection structures are horizontally spaced and penetrate through vertical channels, with upper isolation structures positioned between selection structures. This nested arrangement allows multiple functional components to be integrated within a compact three-dimensional space, increasing storage capacity while managing device complexity through systematic spatial organization.
2Quantity of substance
If more memory cells are integrated to increase storage capacity, then data storage capacity improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent divides the memory structure into segmented components including multiple gate electrodes stacked vertically, horizontally spaced selection structures, and upper isolation structures positioned between selections. This segmentation allows each component to be manufactured and positioned independently with standardized dimensions, reducing overall manufacturing precision requirements while enabling high storage capacity through modular integration.
Solution Approach 2:
The patent applies different structural configurations to different regions: vertical structures penetrate through specific zones, upper isolation structures are positioned in specific locations between selection structures, and horizontal dielectric patterns surround gate electrodes in specific areas. This localized optimization allows manufacturing precision to be concentrated where critical, while other regions provide tolerance buffer zones.
3Productivity
If vertically stacked structures are implemented to improve integration, then integration density improves, but structural stability challenges increase
Solution Approach 1:
The patent employs composite structural configurations combining vertically stacked gate electrodes with horizontally spaced selection structures and upper isolation structures. This composite arrangement distributes mechanical stresses across multiple materials and orientations, enhancing structural stability while maintaining high integration density through the multi-component three-dimensional architecture.
Data Source
AI summary
Disclosed are semiconductor devices and electronic systems including the same. The semiconductor device may include a stack structure extending in a first direction and including gate electrodes vertically stacked on a substrate, selection structures horizontally spaced apart on the stack structure, an upper isolation structure between the selection structure and extending in the first direction on the stack structure, and vertical structures penetrating the stack structure and the selection structures. The vertical structures include first vertical structures arranged along the first direction and penetrating portions of the upper isolation structure. Each selection structure includes a selection gate electrode and a horizontal dielectric pattern that surrounds top, bottom, and sidewall surfaces of the selection gate electrode. Each selection gate electrode includes a line part extending in the first direction, and an electrode part vertically protruding from the line part and surrounding at least a portion of each first vertical structure.