Semiconductor Device Vertical Stacking for Miniaturization
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Solution Overview
Problem
Conventional semiconductor devices with multiple chips integrated into a single package face challenges in miniaturization due to the large horizontal area requirement, which complicates assembly and makes it difficult to achieve both miniaturization and secure insulation distances between high-voltage and low-voltage components.
Innovation Solution
A semiconductor device configuration where two semiconductor chips with different power supply voltages are arranged vertically within a single package, with non-overlapping chip and mounting part positions, and secured by a sealing body, allowing for miniaturization while maintaining necessary insulation distances through the use of inductive coupling and die bonding materials.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If parts of the semiconductor chips are arranged as to overlap with each other in plan view, then the package size in horizontal direction is miniaturized, but the assembly of the semiconductor device becomes difficult
Solution Approach 1:
The patent transitions from a two-dimensional planar arrangement to a three-dimensional stacked arrangement. Multiple semiconductor chips are mounted on different levels (first chip mounting part and second chip mounting part at different heights), allowing horizontal miniaturization without overlapping in plan view, thus facilitating assembly while achieving compact packaging.
2Ease of manufacture
If the semiconductor chips are arranged side by side in horizontal direction, then the assembly is easy, but the package area becomes large
Solution Approach 1:
The patent employs vertical stacking to reduce horizontal footprint. Instead of arranging chips side by side in the same plane, chips are positioned at different vertical levels (first and second chip mounting parts at different heights), maintaining assembly simplicity while minimizing package area.
Solution Approach 2:
The patent implements a nested arrangement where semiconductor chips are positioned within the vertical profile of the package structure. The first and second chips are nested at different height levels within the sealing body, maximizing space utilization and reducing overall package dimensions.
3Adaptability or versatility
If multiple semiconductor chips with different power supply voltages are integrated into a single package, then the device functionality is enhanced, but the insulation distance requirement complicates the miniaturization
Solution Approach 1:
The patent uses vertical separation to satisfy insulation requirements. High-voltage and low-voltage chips are mounted at different vertical levels (first and second chip mounting parts separated in the height direction), providing natural insulation through vertical spacing while maintaining compact horizontal dimensions.
Solution Approach 2:
The patent applies different insulation strategies to different voltage domains. The sealing body provides localized insulation between high-voltage and low-voltage regions, with specific attention to insulation distances in vertical cross-sections where voltage differences exist, allowing miniaturization while maintaining safety margins.
Data Source
AI summary
Miniaturization of a semiconductor device is attained. An SOP1 includes: a semiconductor chip; another semiconductor chip; a die pad over which the former semiconductor chip is mounted; another die pad over which the latter semiconductor chip is mounted; a plurality of wires; and a sealing body. In plan view of the SOP1, the former semiconductor chip and the former die pad do not overlap the latter semiconductor chip and the latter die pad. Also, in a horizontal direction in cross sectional view, the former semiconductor chip and the former die pad do not overlap the latter semiconductor chip and the latter die pad.